On-chip electrical coil and three-dimensional on-chip magnetic sensor including on-chip electrical coil

An on-chip electrical coil comprising:

• a semiconductor substrate;
• a plurality of metal layers disposed on the semiconductor substrate;
• a plurality of insulator layers disposed on the semiconductor substrate, each insulator layer disposed between a pair of neighboring metal layers to form an alternating arrangement of metal layers and insulator layers;
• a plurality of metal vias defined in the insulator layers, each metal via electrically connecting a respective pair of neighboring metal layers;
• and
• a planar spiral formed by the metal layers and the metal vias, the planar spiral including a plurality of interconnected loops, each interconnected loop including two metal wires disposed in respective metal layers, an intra-loop column that electrically connects the two metal wires of a respective interconnected loop, and an inter-loop column that electrically connects one of the metal wires of the respective interconnected loop to one of the metal wires in a subsequent interconnected loop,
• wherein:
• the plurality of interconnected loops includes first and second interconnected loops,
• the two metal wires of the second interconnected loop are located between the two metal wires of the first interconnected loop,
• the two metal wires of the first interconnected loop include an upper metal wire disposed in an upper metal layer and a lower metal wire disposed in a lower metal layer,
• the two metal wires of the second interconnected loop include a third metal wire disposed in a third metal layer and a fourth metal wire disposed in a fourth metal layer, the third and fourth metal layers between the upper and lower metal layers,
• the first interconnected loop includes a first intra-loop column that electrically connects the upper and lower wires, the first intra-loop column including at least:
• a first metal segment of the third metal layer,
• a first metal segment of the fourth metal layer,
• a first metal via that electrically connects the upper metal wire to the first metal segment of the third metal layer,
• a second metal via that electrically connects the first metal segment of the third metal layer to the first metal segment of the fourth metal layer, and
• a third metal via that electrically connects the first metal segment of the fourth metal layer to the lower metal wire, and
• the first interconnected loop includes a first inter-loop column that electrically connects the upper metal wire to the fourth metal wire, the first inter-loop column including at least:
• a second metal segment of the third metal layer,
• a third metal via that electrically connects the upper metal wire to the second metal segment of the third metal layer, and
• a fourth metal via that electrically connects the second metal segment of the third metal layer to the fourth metal wire.