High-throughput scan architecture

An electronic device comprising:

• a clock controller that provides multiple clock signals including a first clock signal at a first frequency and a second clock signal at a second frequency that is less than the first frequency;
• a decompressor configured to receive the first clock signal and provide a first data signal having a set of values, wherein the decompressor is configured to output the values of the first data signal at a first data rate based on the first frequency of the first clock signal;
• a scan chain comprising a two distinct sets of latches provided as a first series of latches and a second series of latches,
• wherein the first series of latches and the second series of latches are both configured to receive the first data signal but capture different subsets of values from the first data signal,
• wherein first series of latches and the second series of latches both receive the second clock signal and capture values from the first data signal at a second data rate based on the second frequency of the second clock signal, and
• wherein the scan chain is configured to provide a second data signal that combines output of the first series of latches with output of the second series of latches;
• and
• a compressor configured to receive the first clock signal and obtain the second data signal from the scan chain, wherein the compressor is configured to obtain the second data signal from the scan chain at the first data rate in accordance with the first frequency using the first clock signal.