Device variation extraction chip
AssigneeShanghai Hauli Integrated Circuit Corporation
InventorsPinhan Chen, Huafeng Wu
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Abstract
The present application discloses a device variation extraction chip, including m MOS devices and one test key, where the test key has 2n pads; a drain of the (k(n−1)+i)-th MOS device is short-circuited with the i-th pad of the test key; a gate of the (k(n−1)+i)-th MOS device is short-circuited with the (n−1+i)-th pad of the test key; a source of each of the m MOS devices is short-circuited with the (2n−1)-th pad; a bulk of each of the m MOS devices is short-circuited with the 2n-th pad. The device variation extraction chip can save the chip area, save the test time, obtain a large amount of data, and improve the accuracy of the obtained device variation and device mismatch, without the addition of a photomask and process node steps.
Claims5
A device variation extraction chip, comprising m metal-oxide semiconductor (MOS) devices and one test key, wherein
- the test key has 2n pads, n is an integer greater than 4, and m is an integer greater than n−1 and less than or equal to (n−1)2;
- a drain of the (k(n−1)+i)th MOS device is short-circuited with the ith pad of the test key, i is a positive integer less than or equal to n−1, and k is a natural number less than or equal to n−2;
- a gate of the (k(n−1)+i)th MOS device is short-circuited with the (n−1+i)th pad of the test key;
- a source of each of the m MOS devices is short-circuited with the (2n−1)th pad;
- a bulk of each of the m MOS devices is short-circuited with the 2nth pad.
Dependencies are inferred from the claim text.