Memory device including arrangement of independently and concurrently operable tiles of memory transistors

A memory device, comprising:

• a plurality of tiles of memory circuits, each tile comprising a physically isolated array of storage transistors (“memory array”) electrically coupled to and operated by a modular control circuit, the memory array comprising a three-dimensional array of storage transistors being organized in a plurality of memory pages of storage transistors, each storage transistor being accessed by a word line and a bit line, the modular control circuit being in communication with the memory array to perform memory operations on one or more memory pages of storage transistors,
• wherein each tile is configurable to be individually addressed and independently operated by the associated modular control circuit to perform memory operations in units of memory pages of storage transistors in the memory array in response to memory access commands designated for the tile, and wherein two or more randomly addressed tiles of memory circuits are configurable to perform overlapping memory operation simultaneously;
• and
• wherein the modular control circuits of the plurality of tiles interact with a memory controller integrated circuit formed on a separate semiconductor substrate, each modular control circuit in a tile receiving a memory access command designated to the tile with a memory address associated with the command, and the memory address designating one memory page in the memory array for performing a memory operation specified by the memory access command;
• and each physically isolated memory array in each tile comprises a three-dimensional array of NOR memory strings of randomly accessible storage transistors, and one or more staircase structures connecting bit lines of the NOR memory string to the modular control circuit, and each modular control circuit in the plurality of tiles are replicated complete control circuit for each tile;
• and
• wherein each modular control circuit comprises bit line driver circuits coupled to the bit lines of the memory array through the staircase structures, the bit line driver circuits selecting bit lines of a memory page designated by the memory address and drive bias voltages in response to the memory operation specified by the memory access command;
• and word line driver circuits coupled to select a word line of the memory array to activate a first number of memory pages of storage transistors, wherein the bit line driver circuits are placed in a portion of the modular control circuit under the staircase structures of the memory array and the word line driver circuits are placed in a center portion of the modular control circuit.