Semiconductor chip package with through electrode configuration under recessed connection pad

A semiconductor package comprising:

• a first semiconductor chip comprising:
• a first substrate comprising a front surface and a rear surface facing each other;
• a first insulating layer disposed on an upper surface of the first substrate;
• a recess portion extending into the first substrate through the first insulating layer;
• a protective insulating layer covering an inner side surface of the recess portion and a bottom surface of the recess portion;
• a through electrode protruding farther than the bottom surface of the recess portion through at least a portion of the first substrate;
• and
• a first connection pad disposed in the recess portion, extending from the rear surface and having a lower surface contacting an upper surface of the through electrode between the front surface and the rear surface of the first substrate, the first connection pad being surrounded by the protective insulating layer;
• and
• a second semiconductor chip disposed on the first semiconductor chip, the second semiconductor chip comprising:
• a second insulating layer contacting the first insulating layer, and
• a second connection pad disposed in the second insulating layer and contacting the first connection pad,
• wherein a thickness of the first insulating layer in a direction perpendicular to the upper surface of the first substrate is greater than a thickness of the protective insulating layer in a direction perpendicular to the inner side surface of the recess portion or the bottom surface of the recess portion.

A semiconductor package comprising:

• a first semiconductor chip comprising:
• a first substrate;
• a first insulating layer disposed on the first substrate;
• a plurality of recess portions extending into the first substrate through the first insulating layer;
• a plurality of protective insulating layers, each of the plurality of protective insulating layers covering an inner side surface and a bottom surface of a respective one of the plurality of recess portions;
• and
• a first connection pad and a first dummy pad respectively disposed in the plurality of recess portions, the first connection pad and the first dummy pad being surrounded by a respective one of the plurality of protective insulating layers, the first semiconductor chip comprising an upper surface defined by an upper surface of the first insulating layer, an upper surface of each of the plurality of protective insulating layers, an upper surface of the first connection pad, and an upper surface of the first dummy pad;
• and
• a second semiconductor chip disposed on the first semiconductor chip, the second semiconductor chip comprising:
• a second insulating layer contacting the first insulating layer;
• a second connection pad disposed in the second insulating layer and contacting the first connection pad;
• and
• a second dummy pad disposed in the second insulating layer and contacting the first dummy pad,
• wherein, on a plane parallel to the upper surface of the first semiconductor chip, a planar shape of the first dummy pad is different from a planar shape of the first connection pad.