Through substrate via landing on front end of line structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChieh-En Chen, Chen-Hsien Lin, Shyh-Fann Ting, Dun-Nian Yaung
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AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChieh-En Chen, Chen-Hsien Lin, Shyh-Fann Ting, Dun-Nian Yaung
Estimating the term…
The problem of connecting a TSV to a BEOL metal interconnect structure without damaging the BEOL metal interconnect structure is solved by landing the TSV on a metal coupling structure formed during FEOL processing. The metal coupling structure is produced in accordance with design rules that apply to FEOL processing. The metal coupling structure may include substructures that have the composition and shape of wires in a transistor level metal interconnect and substructures that have the composition and shape of metal gate strips. The metal coupling structure may include pluralities of the substructures arrayed across the TSV landing area. The substructures that make up the metal coupling structure are connected to the BEOL metal interconnect through vias.
An integrated circuit device, comprising:
An integrated circuit device, comprising:
A method of manufacturing an integrated circuit device, the method comprising:
Dependencies are inferred from the claim text.