Method of forming a hall sensor with performance control
AssigneeTexas Instruments Incorporated
InventorKeith R. Green
Life of this patent
Estimating the term…
Abstract
A Hall sensor includes a Hall well, such as an implanted region in a surface layer of a semiconductor structure, and four doped regions spaced apart from one another in the implanted region. The implanted region and the doped regions include majority carriers of the same conductivity type. The sensor also includes a dielectric layer that extends over the implanted region, and an electrode layer over the dielectric layer to operate as a control gate to set or adjust the sensor performance. A first supply circuit provides a first bias signal to a first pair of the terminals, and a second supply circuit provides a second bias signal to the electrode layer.
Claims15
A method, comprising:
- performing a first implantation process that implants dopants to form an implanted region having a first conductivity type in a semiconductor surface layer over a semiconductor substrate that includes a buried layer having an opposite second conductivity type;
- performing a second implantation process that implants dopants to form first, second, third, and fourth doped regions having the first conductivity type spaced apart from one another in the implanted region, wherein the implanted region extends laterally directly between the first, second, third, and fourth doped regions at a top surface of the semiconductor surface layer;
- forming a dielectric layer over the implanted region;
- and
- forming an electrode layer over the dielectric layer that extends contiguously over the first, second, third, and fourth doped regions and includes five sides that at least partially overlap the first doped region.
A method of forming a semiconductor device, comprising:
- forming an epitaxial layer over a semiconductor substrate, the epitaxial layer including a semiconductor surface layer having a first conductivity type, a first buried layer having an opposite second conductivity type and a second buried layer having the first conductivity type between the semiconductor surface layer and the first buried layer, and
- implanting a dopant into the semiconductor surface layer thereby forming an implanted region, the implanted region extending to a top surface of the semiconductor surface layer and touching the second buried layer and having the second conductivity type and a first dopant concentration;
- forming first, second, third, and fourth terminals that electrically contact the implanted region at respective first, second, third, and fourth locations spaced apart from one another, each of the first, second, third, and fourth terminals including a corresponding first doped portion having the second conductivity type and a second dopant concentration in a corresponding second doped portion having the second conductivity type and a third dopant concentration greater than the first dopant concentration, the second dopant concentration greater than the third dopant concentration and the implanted region extending directly between the second doped portions and the second buried layer;
- forming a dielectric layer that touches the implanted region and the second doped portions;
- and
- forming a contiguous electrode layer that touches the dielectric layer and extends over the second doped portions, the electrode layer including five sides that overlap a first one of the second doped portions.
Dependencies are inferred from the claim text.