Fork sheet with reduced coupling effect
AssigneeInternational Business Machines Corporation
InventorsRuilong Xie, Chun-Chen Yeh, Heng Wu, Alexander Reznicek
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Abstract
Fork sheet FET devices with airgap isolation are provided. In one aspect, a fork sheet FET device includes: at least a first nanosheet FET and a second nanosheet FET; and a dielectric pillar disposed directly between the first nanosheet FET and the second nanosheet FET, wherein the dielectric pillar includes an airgap. For instance, the first nanosheet FET and the second nanosheet FET can have nanosheets that extend horizontally on opposite sides of the dielectric pillar. A method of forming a fork sheet FET device having airgap isolation is also provided.
Claims11
A fork sheet field-effect transistor (FET) device, comprising:
- at least a first nanosheet FET and a second nanosheet FET, wherein the first nanosheet FET comprises an n-channel FET (NFET) and the second nanosheet FET comprises a p-channel FET (PFET);
- and
- a dielectric pillar disposed directly between the first nanosheet FET and the second nanosheet FET, wherein the dielectric pillar is an airgap pillar and wherein the dielectric pillar is a vertical continuous and hollow structure further comprising:
- a top portion of the dielectric pillar;
- a bottom portion of the dielectric pillar embedded into a substrate;
- and
- a continuous and uninterrupted vertical wall connecting the top portion of the dielectric pillar to the bottom portion of the dielectric pillar by forming a right angle at an intersection between the top portion of the dielectric pillar and the bottom portion of the dielectric pillar and wherein the bottom portion of the dielectric pillar has a width W1 and the top portion of an opening has a width W2 and wherein W2<W1.
A fork sheet field-effect transistor (FET) device, comprising:
- at least a first nanosheet FET and a second nanosheet FET;
- and
- a dielectric pillar disposed directly between the first nanosheet FET and the second nanosheet FET, wherein the dielectric pillar is an airgap pillar, and wherein the first nanosheet FET and the second nanosheet FET comprise nanosheets that extend horizontally on opposite sides of the dielectric pillar, wherein the dielectric pillar is a vertical and hollow structure further comprising:
- a top portion of the dielectric pillar;
- a bottom portion of the dielectric pillar embedded into a substrate;
- and
- a continuous and uninterrupted vertical wall connecting the top portion of the dielectric pillar to the bottom portion of the dielectric pillar by forming a right angle at an intersection between the top portion of the dielectric pillar and the bottom portion of the dielectric pillar and wherein the bottom portion of the dielectric pillar has a width W1 and the top portion of an opening has a width W2 and wherein W2<W1.
Dependencies are inferred from the claim text.