Method for forming semiconductor structure

A method for forming a semiconductor structure, comprising:

• forming a first plurality of nanostructures over a lower fin element;
• forming a source/drain feature over the lower fin element to abut the first plurality of nanostructures;
• forming an interlayer dielectric layer over the source/drain feature;
• forming a first gate stack to surround the first plurality of nanostructures;
• forming a spacer layer between the first gate stack and the source/drain feature;
• and
• forming a gate cutting structure in the spacer layer, the first gate stack and the interlayer dielectric layer, wherein the gate cutting structure includes a first protruding portion which extends a first distance from a first sidewall of the gate cutting structure toward the first plurality of nanostructures in a first direction that is parallel to a longitudinal axis of the first gate stack.

A method for forming a semiconductor structure, comprising:

• forming a first plurality of channel layers over a first fin element;
• forming a second plurality of channel layers over a second fin element;
• forming a first source/drain feature over the first fin element;
• forming a second source/drain feature over the second fin element;
• forming a gate stack across the first fin element and the second fin element, wherein the gate stack wraps around the first plurality of channel layers and the second plurality of channel layers;
• and
• forming a gate cutting structure through the gate stack, wherein:
• the gate cutting structure has a first edge between the first plurality of channel layers and the second plurality of channel layers and a second edge between the first source/drain feature and the second source/drain feature, and
• in a top view, the first edge is offset from the second edge by a distance, and the first edge is connected to the second edge through a third edge of the gate cutting structure.