Footing removal in cut-metal process
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMing-Chi Huang, Kuo-Bin Huang, Ying-Liang Chuang, Ming-Hsi Yeh
Life of this patent
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Abstract
A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.
Claims20
A structure comprising:
- a gate spacer;
- a first transistor comprising:
- first portions of the gate spacer;
- a first gate stack between the first portions of the gate spacer, the first gate stack comprising:
- a first gate dielectric, wherein an extension portion of the first gate dielectric is directly underlying, and overlapped by, a top portion of the gate spacer, wherein in a cross-sectional view of the structure, the extension portion of the first gate dielectric has a L-shape comprising:
- a slanted sidewall portion;
- and
- a horizontal portion connected to a bottom end of the slanted sidewall portion;
- and
- a first gate electrode over a first portion of the first gate dielectric;
- a second transistor comprising:
- second portions of the gate spacer;
- a second gate stack between the second portions of the gate spacer, the second gate stack comprising:
- a second gate dielectric;
- and
- a second gate electrode over a second portion of the second gate dielectric;
- a dielectric isolation region between the first portions and the second portions of the gate spacer, wherein the dielectric isolation region is physically joined to the first gate electrode and the second gate electrode, wherein a lower portion of the dielectric isolation region is underlying and overlapped by the top portion of the gate spacer, and wherein the lower portion of the dielectric isolation region is directly underlying and overlapped by the slanted sidewall portion;
- and
- a polymer layer comprising a first portion contacting the dielectric isolation region, wherein in a cross-section of the dielectric isolation region and the polymer layer, a first topmost surface of the first portion of the polymer layer is lower than a second topmost surface of the dielectric isolation region.
A structure comprise:
- a first gate spacer, wherein the first gate spacer comprises an upper portion and a lower portion;
- a second gate spacer parallel to the first gate spacer;
- a first gate stack between the first gate spacer and the second gate spacer;
- a second gate stack between the first gate spacer and the second gate spacer;
- a dielectric region between the first gate stack and the second gate stack, and between the first gate spacer and the second gate spacer, wherein the dielectric region comprises:
- a high-k dielectric layer, wherein a portion of the high-k dielectric layer is in physical contact with the lower portion of the first gate spacer, and wherein the portion of the high-k dielectric layer is overlapped and covered by the upper portion of the first gate spacer;
- a shallow trench isolation region directly underlying the dielectric region;
- and
- a polymer layer comprising a first portion between the dielectric region and the shallow trench isolation region.
A structure comprise:
- a first gate spacer, wherein the first gate spacer comprises an upper portion and a lower portion;
- a second gate spacer parallel to the first gate spacer;
- a first gate stack between the first gate spacer and the second gate spacer;
- a second gate stack between the first gate spacer and the second gate spacer;
- a dielectric isolation region separating the first gate stack from the second gate stack;
- a first portion of a polymer layer underlying and contacting the dielectric isolation region;
- and
- a second portion of the polymer layer aside of and contacting the dielectric isolation region, wherein the second portion of the polymer layer is physically separated from the first portion of the polymer layer.
Dependencies are inferred from the claim text.