Semiconductor structure with dielectric wall structure and method for manufacturing the same

A method for manufacturing a semiconductor structure, comprising:

• forming a first well region, a second well region, a third well region, and a fourth well region in a substrate;
• stacking first semiconductor material layers and second semiconductor material layers to form a semiconductor stack over the substrate;
• patterning the semiconductor stack and the substrate to form a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure in the first well region, the second well region, the third well region, and the fourth well region, respectively, wherein the first fin structure, the second fin structure, the third fin structure, and the fourth fin structure are longitudinally oriented along a first direction and are sequentially arranged in a second direction different from the first direction, and the second fin structure is wider than the third fin structure in the second direction;
• forming a dielectric wall structure sandwiched between the first fin structure and the second fin structure over a boundary between the first well region and the second well region;
• removing the first semiconductor material layers of the first fin structure, the second fin structure, the third fin structure, and the fourth fin structure to form first channel structures, second channel structures, third channel structures, and fourth channel structures, respectively;
• and
• forming a gate structure wrapping around the first channel structures, the second channel structures, the third channel structures, and the fourth channel structures,
• wherein a distance between the third channel structures and the fourth channel structures is greater than a width of the dielectric wall structure in the second direction.

A semiconductor structure, comprising:

• a first well region, a second well region, a third well region, and a fourth well region formed in a substrate, wherein the first well region and the fourth well region comprise first dopants, and the second well region and the third well region comprise second dopants different from the first dopants;
• a dielectric wall structure formed over a boundary of the first well region and the second well region and longitudinally oriented along a first direction;
• first channel structures, second channel structures, third channel structures, and fourth channel structures vertically suspended over the first well region, the second well region, the third well region, and the fourth well region respectively, wherein the first channel structures are attached to a first sidewall surface of the dielectric wall structure, and the second channel structures are attached to a second sidewall surface of the dielectric wall structure;
• and
• a first gate structure longitudinally oriented along a second direction being substantially orthogonal to the first direction,
• wherein the first channel structures have a first width in the second direction the second channel structures have a second width in the second direction, the third channel structures have a third width in the second direction, the fourth channel structures have a fourth width in the second direction, the second width is greater than the third width, and the first width is greater than the fourth width and smaller than the third width.