Semiconductor memory structure with contact passing through opening in control gate

A semiconductor device, comprising:

• a substrate, having a first memory region,
• wherein the first memory region comprises:
• a first dielectric layer, disposed on the substrate;
• a first floating gate, disposed on the first dielectric layer;
• a first inter-gate dielectric layer, disposed on the first floating gate;
• a first control gate, disposed on the first inter-gate dielectric layer;
• and
• a first contact, penetrating through the first control gate and the first inter-gate dielectric layer, and landed on the first floating gate, and
• the substrate further comprises a second memory region,
• wherein the second memory region comprises:
• a second dielectric layer, disposed on the substrate;
• a second floating gate, disposed on the second dielectric layer;
• a second inter-gate dielectric layer, disposed on the second floating gate;
• a second control gate, disposed on the second inter-gate dielectric layer;
• and
• a second contact, landed on the second control gate.