Silicon carbide semiconductor device

A silicon carbide semiconductor device, comprising:

• a semiconductor substrate containing silicon carbide, the semiconductor substrate having an active region and a termination region that surrounds a periphery of the active region in a top view of the silicon carbide semiconductor device, the semiconductor substrate having a first main surface and a second main surface that are opposite to each other;
• a first parallel pn layer provided in the semiconductor substrate in the active region, the first parallel pn layer having disposed therein a plurality of first first-conductivity-type regions and a plurality of first second-conductivity-type regions repeatedly alternating with one another in a first direction that is parallel to the first main surface of the semiconductor substrate;
• a second parallel pn layer provided in the semiconductor substrate, adjacent to the first parallel pn layer and in the termination region, the second parallel pn layer having disposed therein a plurality of second first-conductivity-type regions and a plurality of second second-conductivity-type regions repeatedly alternating with one another in the first direction;
• a device structure provided in the active region, between the first main surface of the semiconductor substrate and the first parallel pn layer;
• a first electrode provided on the first main surface of the semiconductor substrate, and electrically connected to the device structure;
• a second electrode provided on the second main of the semiconductor substrate;
• a first semiconductor region of a second conductivity type electrically connected to the first electrode, the first semiconductor region being selectively provided in the termination region, between the first main surface of the semiconductor substrate and the second parallel pn layer, and surrounding the periphery of the active region, the second parallel pn layer being provided apart from the first semiconductor region, at a position deeper from the first main surface of the semiconductor substrate than is the first semiconductor region and closer to an end of the semiconductor substrate than is an outer end of the first semiconductor region;
• a second semiconductor region of a first conductivity type, provided between the second parallel pn layer and the first semiconductor region, and in contact with the first semiconductor region;
• and
• a channel stopper region configuring a voltage withstanding structure with the first semiconductor region, the channel stopper region being disposed apart from the first semiconductor region and closer to the end of the semiconductor substrate than is the first semiconductor region, wherein
• the second semiconductor region has a portion that is disposed between the channel stopper region and the second parallel pn layer, and separates the channel stopper region from the second parallel pn layer, and
• upper ends of the plurality of second second-conductivity-type regions are flat.