Shielded gate transistor

A method for fabricating a transistor on a substrate, the method comprising:

• forming a device layer over the substrate;
• forming a first gate electrode over the device layer;
• forming a drain electrode over the substrate adjacent to the device layer and spaced from the gate electrode;
• forming a first source electrode over the substrate adjacent to the device layer opposed from the drain electrode and spaced from the gate electrode;
• forming a second source electrode over the substrate and spaced from the drain electrode on a side of the drain electrode opposed from the gate electrode;
• disposing a dielectric over the substrate between the first source electrode and the second electrode, wherein the dielectric extends over the device layer, the gate electrode, and the drain electrode;
• forming a conductive interconnect coupling the first source electrode and the second source electrode and extending over the dielectric, wherein the conductive interconnect comprises a first shield wall that extends from the conductive interconnect into the dielectric between the first gate electrode and the drain electrode with a distal end that is spaced above the device layer, wherein the first shield wall is configured to intercept an electric field that would form between the first gate electrode and the drain electrode if the first shield wall did not exist.

A wireless communication device comprising:

• a baseband processor;
• transmit circuitry configured to receive encoded data from the baseband processor and to modulate a carrier signal with the encoded data, wherein the transmit circuitry comprises:
• a substrate;
• a device layer disposed over the substrate;
• a first gate electrode disposed over the device layer;
• a drain electrode disposed over the substrate adjacent to the device layer and spaced from the first gate electrode;
• a first source electrode disposed over the substrate adjacent to the device layer opposed from the drain electrode and spaced from the gate electrode;
• a second source electrode disposed over the substrate and spaced from drain electrode on a side of the drain electrode opposed from the gate electrode;
• a dielectric disposed over the substrate between the first source electrode and the second electrode, wherein the dielectric extends over the device layer, the gate electrode, and the drain electrode;
• and
• a conductive interconnect coupling the first source electrode and the second source electrode and extending over the dielectric, wherein the conductive interconnect comprises a first shield wall that extends from the conductive interconnect into the dielectric between the gate electrode and the drain electrode with a distal end that is spaced above the device layer, wherein the first shield wall is configured to intercept an electric field that would form between the first gate electrode and the drain electrode if the first shield wall did not exist.