US 12,635,163 B2Granted

Method to produce a 3D multilayer semiconductor device and structure

AssigneeMonolithic 3D Inc.

InventorsZvi Or-Bach, Jin-Woo Han

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Abstract

Methods of making a 3D multilayer semiconductor device, including: providing a first substrate including a first level, the first level including a first single crystal silicon layer (SCSL); providing a second substrate including a second level, the second level including a second SCSL; performing an epitaxial growth of a SiGe layer on top of the second SCSL; performing an epitaxial growth of a third SCSL on top of the SiGe layer, the third SCSL has an average thickness of less than 2,000 nm; forming second transistors each including a single crystal channel, where forming the second transistors includes growth of a second SiGe layer on top of the third SCSL; forming many metal layers interconnecting the second transistors; and then performing a bonding of the second level onto the first level, where performing the bonding includes making oxide-to-oxide bond zones; and performing removal of a majority of the second SCSL.

Claims20

Dependent claims

A method of making a 3D multilayer semiconductor device, the method comprising:

providing a first substrate comprising a first level, said first level comprising a first single crystal silicon layer;
providing a second substrate comprising a second level, said second level comprising a second single crystal silicon layer;
performing an epitaxial growth of a first SiGe layer on top of said second single crystal silicon layer;
performing an epitaxial growth of a third single crystal silicon layer on top of said SiGe layer,
wherein said third single crystal silicon layer has an average thickness of less than 2,000 nm;
forming a plurality of second transistors each comprising a single crystal channel;
wherein said forming a plurality of second transistors comprise performing an epitaxial growth of a second SiGe layer on top of said third single crystal silicon layer;
performing an epitaxial growth of a third single crystal silicon layer on top of said SiGe layer;
forming a plurality of metal layers interconnecting said plurality of second transistors;
and then
performing a bonding of said second level onto said first level,
wherein performing said bonding comprises making oxide-to-oxide bond zones;
and
performing removal of a majority of said second single crystal silicon layer.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/320,623Filed 5 Sep 2025 · continuation in part
Priority: 21 Sep 2015
Published: US 2026/0006819 A11 Jan 2026
Granted: 19 May 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification37 codes

H10B 20/25
Programmable ROM [PROM] devices comprising field-effect components: one-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
H10D 30/0411
Of FETs having insulated gates [IGFET]: of FETs having floating gates
H10B 41/23
Characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels: with source and drain on different levels, e.g.…
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels

Family

Application62/221,618Us provisional application · filed 21 Sep 2015
PCT/US2016/052726Parent of this continuation-in-part · filed 21 Sep 2016
Application16/224,674Parent of this continuation-in-part · filed 18 Dec 2018
US 10,515,981 B2Parent of this continuation-in-part · filed 24 Dec 2019
Application16/797,231Parent of this continuation-in-part · filed 21 Feb 2020
Application18/622,992Parent of this continuation-in-part · filed 31 Mar 2024
US 11,978,731 B2Parent of this continuation-in-part · filed 7 May 2024
Application18/793,939Parent of this continuation-in-part · filed 5 Aug 2024
US 12,100,658 B2Parent of this continuation-in-part · filed 24 Sep 2024
US 2026/0006819 A1Pre-grant publication · published 1 Jan 2026
US 12,432,926 B2Parent of this continuation-in-part
Application15/761,426Parent of this continuation-in-part
US 2018/0269229 A1Published application
US 2019/0148286 A1Published application
US 2020/0194416 A1Published application
US 2024/0274534 A1Published application
US 2024/0397720 A1Published application
US 12,635,163 B2This patent

From the US filing history. Foreign family members aren’t listed.