Stacked multi-gate device with barrier layers

A method, comprising:

• epitaxially growing a plurality of first semiconductor layers and a plurality of second semiconductor layers on a substrate, the first semiconductor layers and the second semiconductor layers interleaving each other in a vertical direction;
• forming a plurality of barrier layers interposing adjacent ones of the first and second semiconductor layers;
• patterning the first and second semiconductor layers and the barrier layers to form a fin-shaped structure;
• replacing a middle one of the second semiconductor layers with a dielectric layer, wherein the dielectric layer is sandwiched by two of the barrier layers;
• removing the second semiconductor layers above and under the dielectric layer;
• forming a first gate structure wrapping around a bottom portion of the first semiconductor layers under the dielectric layer;
• and
• forming a second gate structure wrapping around a top portion of the first semiconductor layers above the dielectric layer.

A semiconductor device, comprising:

• a plurality of first nanostructures;
• a lower source/drain feature abutting the first nanostructures;
• a first gate structure wrapping around each of the first nanostructures;
• a dielectric layer disposed above the first nanostructures;
• a plurality of second nanostructures disposed above the dielectric layer;
• an upper source/drain feature abutting the second nanostructures;
• a second gate structure wrapping around each of the second nanostructures;
• a first barrier layer directly interfacing a top surface of the dielectric layer;
• and
• a second barrier layer directly interfacing a bottom surface of the dielectric layer.