Gallium nitride superjunction transistor
AssigneeAnalog Devices, Inc.
InventorsJames G. Fiorenza, Guanghai Ding, Daniel Piedra
Life of this patent
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Abstract
Techniques to increase the number of current paths (or “channels”) in a GaN transistor, without increasing the device area, thereby decreasing the on-resistance. In addition, this disclosure describes techniques to utilize back-side field management to improve the device's performance. For example, the techniques can include using p-type implantation into the substrate, e.g., silicon carbide (SiC), as a field management tool to form a superjunction device, thereby increasing the effective field and reducing the on-resistance multiplied by the output charge (Qoss).
Claims18
A compound semiconductor heterostructure transistor device having multiple two-dimensional electron gas channels, the compound semiconductor heterostructure transistor device comprising:
- a substrate;
- a first semiconductor material layer formed over the substrate;
- a second semiconductor material layer formed over the first semiconductor material to form a first compound semiconductor heterostructure having a buried first two-dimensional electron gas (2DEG) channel, wherein the buried first 2DEG channel is more electrically conductive than either the first semiconductor material layer or the second semiconductor material layer;
- a third semiconductor material layer formed over a fourth semiconductor material layer, wherein the fourth semiconductor material layer is formed over the substrate, to form a second compound semiconductor heterostructure having a topside second 2DEG channel, wherein the topside second 2DEG channel is more electrically conductive than either the third semiconductor material layer or the fourth semiconductor material layer;
- a drain electrode electrically coupled to the first semiconductor material layer;
- a source electrode electrically coupled to the topside second 2DEG channel;
- and
- a gate electrode formed over the third semiconductor material layer, wherein the gate electrode is associated with only the topside second 2DEG channel and not associated with the buried first 2DEG channel;
- and
- a conductive material extending vertically and electrically coupling 1) the buried first 2DEG channel and 2) the topside second 2DEG channel, wherein a current through the buried first 2DEG channel is approximately the same as a current through the topside second 2DEG channel.
A method of forming a compound semiconductor heterostructure transistor device, the method comprising:
- forming a first semiconductor material layer over a substrate;
- forming a second semiconductor material layer over the first semiconductor material layer to form a first compound semiconductor heterostructure having a buried first two-dimensional electron gas (2DEG) channel, wherein the buried first 2DEG channel is more electrically conductive than either the first semiconductor material layer or the second semiconductor material layer;
- forming a third semiconductor material layer over a fourth semiconductor material layer, wherein the fourth semiconductor material layer is formed over the substrate, to form a second compound semiconductor heterostructure having a topside second 2DEG channel, wherein the topside second 2DEG channel is more electrically conductive than either the third semiconductor material layer or the fourth semiconductor material layer;
- forming a drain electrode electrically coupled to the first semiconductor material layer;
- forming a source electrode electrically coupled to only the topside second 2DEG channel;
- and
- forming a gate electrode over the third semiconductor material layer;
- and
- forming a conductive material that extends vertically and electrically couples 1) the buried first 2DEG channel and 2) the topside second 2DEG channel, wherein a current through the buried first 2DEG channel is approximately the same as a current through the topside second 2DEG channel.
Dependencies are inferred from the claim text.