Semiconductor die stacks and associated systems and methods

A method comprising:

• providing a first wafer including a plurality of first semiconductor dies, each of the first semiconductor dies including a plurality of first conductive components on a front side of the first wafer, the plurality of first conductive components coupled to first circuitry;
• providing a second wafer including a plurality of second semiconductor dies, each of the second semiconductor dies including a plurality of second conductive components on a front side of the second wafer, the plurality of second conductive components coupled to second circuitry;
• bonding the first wafer to the second wafer to form a bonding interface therebetween,
• wherein:
• each of the first conductive components is conjoined to a corresponding one of the second conductive components at the bonding interface;
• and
• each of the first semiconductor dies includes a plurality of through-substrate vias (TSVs) connected to the plurality of first conductive components such that both the first circuitry and the second circuitry are coupled to a plurality of bond pads on a back side of each of the first semiconductor die through the plurality of TSVs
• polishing, after bonding the first wafer to the second wafer, a back side of the first wafer to expose portions of the TSVs from the back side of the first wafer,
• wherein the plurality of TSVs are formed from the front side of the first wafer prior to bonding the first wafer to the second wafer, and wherein the plurality of first conductive components are formed to connect to the plurality of TSVs present on the front side of the first wafer.

A method comprising:

• providing a first wafer including a plurality of first semiconductor dies, each of the first semiconductor dies including a plurality of first conductive components on a front side of the first wafer, the plurality of first conductive components coupled to first circuitry;
• providing a second wafer including a plurality of second semiconductor dies, each of the second semiconductor dies including a plurality of second conductive components on a front side of the second wafer, the plurality of second conductive components coupled to second circuitry;
• bonding the first wafer to the second wafer to form a bonding interface therebetween,
• wherein:
• each of the first conductive components is conjoined to a corresponding one of the second conductive components at the bonding interface;
• and
• each of the first semiconductor dies includes a plurality of through-substrate vias (TSVs) connected to the plurality of first conductive components such that both the first circuitry and the second circuitry are coupled to a plurality of bond pads on a back side of each of the first semiconductor die through the plurality of TSVs,
• the plurality of TSVs are formed from a back side of the first wafer after bonding the first wafer to the second wafer, and
• the plurality of TSVs are formed to connect to the plurality of first conductive components present on the front side of the first wafer.

A semiconductor die assembly, comprising:

• a logic die including logic circuitry, wherein the logic die includes a plurality of first conductive pads on a front side of the logic die, the plurality of first conductive pads coupled to the logic circuitry;
• and
• a memory die including an array of memory cells, wherein the memory die includes a plurality of second conductive pads on a front side of the memory die, the plurality of second conductive pads coupled to the array of memory cells, and wherein;
• the front sides of the logic die and the memory die are directly bonded such that each of the first conductive pads is conjoined to a corresponding one of the second conductive pads at a bonding interface defined by the front sides of the first and second semiconductor dies;
• and
• the logic die includes a plurality of through-substrate vias (TSVs) connected to the plurality of first conductive pads such that the logic circuitry and the array of memory cells are coupled to a plurality of bond pads on a back side of the logic die through the plurality of TSVs,
• wherein the logic circuitry includes a first structure generated using a first process at a first temperature, and
• wherein the array of memory cells includes a second structure generated using a second process at a second temperature less than the first temperature.