Fabricating non-linear polar material based capacitors for memory and logic

A method of fabricating a device, the method comprising:

• forming a multi-layer stack, the forming comprising:
• depositing a first conductive layer;
• depositing a second conductive layer on the first conductive layer;
• depositing a dielectric layer on the second conductive layer;
• depositing a third conductive layer on the dielectric layer;
• depositing a fourth conductive layer comprising ruthenium, platinum and/or iridium on the third conductive layer, wherein depositing the fourth conductive layer comprises performing a sputter or a co-sputter deposition;
• forming a mask on the multi-layer stack;
• and
• patterning the multi-layer stack to form a capacitor device by applying a plasma etch process, the plasma etch process comprising:
• etching the fourth conductive layer to form a hardmask, the hardmask comprising a first slope having a first angle;
• etching the third conductive layer to form a first electrode, the first electrode comprising a second slope having a second angle;
• etching the dielectric layer to form an etched dielectric layer, the etched dielectric layer comprising a third slope having a third angle;
• etching the second conductive layer to form a second electrode, the second electrode comprising a fourth slope having a fourth angle;
• and
• etching the first conductive layer to form a third electrode, the third electrode comprising a fifth slope having a fifth angle, wherein the first angle, the second angle, the third angle, the fourth angle, and the fifth angle are individually measured relative to a normal to a lowermost surface of the second electrode, wherein the second angle is less than the third angle, wherein the third angle is less than the fourth angle, wherein the second angle, the third angle, the fourth angle and the fifth angle are individually less than 10 degrees, and wherein the first angle is less than 30 degrees.

A method of fabricating a memory device, the method comprising:

• forming a conductive interconnect within a dielectric, the conductive interconnect in a first level;
• forming a transition electrode on at least a portion of the conductive interconnect, the transition electrode in a second level, wherein the transition electrode comprises a conductive hydrogen barrier material;
• forming a multi-layer stack in a third level, the forming comprising:
• depositing a first conductive layer;
• depositing a dielectric layer comprising a non-Pb based material on the first conductive layer;
• depositing a second conductive layer on the dielectric layer;
• and
• depositing a third conductive layer comprising one or more of ruthenium, platinum or iridium on the second conductive layer, wherein depositing the third conductive layer comprises performing a sputter or a co-sputter deposition process;
• and
• patterning the multi-layer stack to form the memory device by utilizing a plasma etch process, the plasma etch process comprising:
• etching the third conductive layer to form a hardmask, the hardmask comprising a first slope having a first angle;
• etching the second conductive layer to form a first electrode, the first electrode comprising a second slope having a second angle;
• etching the dielectric layer to form an etched dielectric layer, the etched dielectric layer comprising a third slope having a third angle;
• and
• etching the first conductive layer to form a second electrode, the second electrode comprising a fourth slope having a fourth angle, wherein the first angle, the second angle, the third angle, and the fourth angle are individually measured relative to a normal to a lowermost surface of the second electrode, wherein the second angle is less than the third angle, wherein the third angle is less than the fourth angle, wherein the second angle, the third angle and the fourth angle are individually less than 10 degrees, and wherein the first angle is less than 30 degrees.