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US 12,635,128 B2Granted
Semiconductor structure and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
Life of this patent
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Abstract
A method includes forming a transistor on a front-side of a substrate, the transistor comprising a channel region, a gate structure surrounding the channel region, and source/drain regions on opposite sides of the gate structure; forming a front-side contact on a first one of the source/drain regions of the transistor; forming a back-side contact on a second one of the source/drain regions of the transistor; forming a back-side capacitor on the back-side contact.
Claims20
A method, comprising:
- forming a transistor on a front-side of a substrate, the transistor comprising a channel region, a gate structure surrounding the channel region, and source/drain regions on opposite sides of the gate structure;
- forming a front-side contact on a first one of the source/drain regions of the transistor;
- forming a back-side contact on a second one of the source/drain regions of the transistor;
- and
- forming a back-side capacitor on the back-side contact;
- wherein forming the back-side capacitor comprises:
- forming a dielectric layer over a back-side of the substrate;
- etching the dielectric layer to form an opening;
- forming a bottom electrode layer in the opening such that the bottom electrode layer is electrically to the back-side contact and has a U-shape from a cross-sectional view;
- forming an insulator layer on the bottom electrode layer;
- and
- forming a top electrode layer on the insulator layer.
9 more elements
A method, comprising:
- forming a transistor on a substrate;
- after forming the transistor, flipping the substrate upside down;
- after flipping the substrate, forming a dielectric layer over the substrate;
- etching the dielectric layer to formed an opening;
- and
- forming a capacitor in the opening and electrically connected to the transistor, forming the capacitor comprising:
- forming a bottom electrode layer in the opening such that the bottom electrode layer has a lateral portion lining a bottom surface of the opening and a first vertical portion lining a sidewall of the opening;
- forming an insulator layer on the bottom electrode layer;
- and
- forming a top electrode layer on the insulator layer.
7 more elements
A method, comprising:
- forming a first source/drain region and a second source/drain region separated from the first source/drain region by a first gate;
- forming a front-side source/drain contact coupled to the second source/drain region;
- forming a first back-side source/drain contact coupled to the first source/drain region, wherein the front-side source/drain contact is coupled to a top surface of the second source/drain region and the first back-side source/drain contact is coupled to a bottom surface of the first source/drain region;
- forming a dielectric layer over the first back-side source/drain contact, wherein the dielectric layer defines a first opening;
- and
- forming a bottom electrode in the first opening and coupled to the first back-side source/drain contact.
3 more elements
Dependencies are inferred from the claim text.