US 12,635,122 B2 · Multi-chip memory system including DRAM chips with integrated comparator arrays and method of operating same

Abstract

A memory system including a first chip having a processor, and a second chip having a DRAM sector that includes: a plurality of DRAM arrays; an output circuit configured to store a plurality of data values read from the DRAM arrays; a first set of through silicon vias (TSVs) connecting the processor to the DRAM sector, wherein the first processor transmits a plurality of weight data values to the DRAM sector on the first set of TSVs; a plurality of comparator arrays coupled to receive the plurality of weight data values and the plurality of data values read from the DRAM arrays, and in response, generate a plurality of comparison output values; and a second set of TSVs connecting the processor to the DRAM sector, wherein the plurality of comparison output values are transmitted from DRAM sector to the processor on the second set of TSVs.

Claims20

Dependent claims

A memory system comprising:

a first integrated circuit chip comprising a first processor;
a second integrated circuit chip comprising a first dynamic random access memory (DRAM) sector including:
a first plurality of DRAM arrays;
a first output circuit configured to store a first plurality of data values read from the first plurality of DRAM arrays;
a first set of through silicon vias connecting the first processor to the first DRAM sector, wherein the first processor transmits a first plurality of weight data values to the first DRAM sector on the first set of through silicon vias;
a first plurality of comparator arrays coupled to receive the first plurality of weight data values and the first plurality of data values read from the first plurality of DRAM arrays, and in response, generate a first plurality of comparison output values;
and
a second set of through silicon vias connecting the first processor to the first DRAM sector, wherein the first plurality of comparison output values are transmitted from the first DRAM sector to the first processor on the second set of through silicon vias.

5 more elements

A method comprising

transmitting a first comparison instruction and a corresponding first plurality of weight data values from a first processor on a first integrated circuit chip to a first dynamic random access memory (DRAM) sector on a second integrated circuit chip, wherein the first DRAM sector comprises a first plurality of DRAM arrays;
reading a first plurality of data values from the first plurality of DRAM arrays in response to the first comparison instruction;
generating a first plurality of comparison output values in response to the first plurality of data values and the first plurality of weight data values;
and
transmitting the first plurality of comparison output values from the first DRAM sector to the first processor.

2 more elements

Dependencies are inferred from the claim text.

Multi-chip memory system including DRAM chips with integrated comparator arrays and method of operating same

Life of this patent

Multi-chip memory system including DRAM chips with integrated comparator arrays and method of operating same

Life of this patent

Abstract

Claims20