US 12,634,176 B2 · Decision feedback equalizer for minimizing number of comparators in decoder and operation method thereof

Abstract

Disclosed is a decision feedback equalizer, which includes a summator that receives a gray code-based PAM-4 signal, a first bit signal, and a second bit signal, and outputs an input voltage obtained by adding a preset coefficient to a voltage level of the PAM-4 signal in response to the first bit signal and the second bit signal, and a decoder that receives the input voltage and first to third reference voltages of the PAM-4 signal and outputs the first bit signal and the second bit signal, and the decoder includes a first comparator that outputs the first bit signal by comparing a magnitude of the input voltage with a magnitude of the first reference voltage, and a second comparator that outputs the second bit signal by comparing charge-discharge intensities of the input voltage and the second and third reference voltages.

Claims10

Dependent claims

A decision feedback equalizer comprising:

a summator configured to receive a gray code-based 4-level pulse amplitude modulation (PAM-4) signal, a first bit signal, and a second bit signal, and to output an input voltage obtained by adding a preset coefficient to a voltage level of the PAM-4 signal in response to the first bit signal and the second bit signal;
and
a decoder configured to receive the input voltage, a first reference voltage, a second reference voltage, a third reference voltage of the PAM-4 signal, and to output the first bit signal and the second bit signal,
wherein the decoder includes:
a first comparator configured to output the first bit signal by comparing a magnitude of the input voltage with a magnitude of the first reference voltage;
and
a second comparator configured to output the second bit signal by comparing charge-discharge intensities of the input voltage and the second and third reference voltages.

4 more elements

A method of operating a decision feedback equalizer comprising a summator and a decoder, the method comprising:

receiving, by the summator, a gray code-based 4-level pulse amplitude modulation (PAM-4) signal, a first bit signal, and a second bit signal, and outputting an input voltage obtained by adding a preset coefficient to a voltage level of the PAM-4 signal in response to the first bit signal and the second bit signal;
and
receiving, by the decoder, the input voltage and first to third reference voltages of the PAM-4 signal, and outputting the first bit signal and the second bit signal,
wherein the outputting of the first bit signal and the second bit signal includes:
outputting the first bit signal by comparing a magnitude of the input voltage with a magnitude of the first reference voltage;
and
outputting the second bit signal by comparing charge-discharge intensities of the input voltage and the second and third reference voltages.

4 more elements

Dependencies are inferred from the claim text.

Decision feedback equalizer for minimizing number of comparators in decoder and operation method thereof

Life of this patent

Decision feedback equalizer for minimizing number of comparators in decoder and operation method thereof

Life of this patent

Abstract

Claims10