Computing architecture for energy-efficient hash computation

An apparatus comprising:

• a plurality of data storage circuit elements stored in an array, wherein the plurality of data storage circuit elements store a plurality of words readable as bit line data that are used for hashing a message, wherein a data storage circuit element of the plurality of data storage circuit elements stores a word of the plurality of words during hashing of the message, wherein hashing the message includes using at least one demultiplexer and at least one multiplexer to simulate shifting of the word without rotating from or shifting the word to any other data storage circuit element of the plurality of data storage circuit elements, and wherein the at least one multiplexer receives input from one or more bit lines associated with the plurality of data storage circuit elements;
• a clock circuit element;
• one or more combinational logic circuit elements that cause the at least one multiplexer to select specified data storage circuit elements of the plurality of data storage circuit elements based on a clock input received from the clock circuit element, wherein the one or more combinational logic circuit elements select the specified data storage circuit elements according to a specified order that changes throughout hashing the message;
• and
• one or more computational operators that generate one or more additional words based on the specified data storage circuit elements as selected by the one or more combinational logic circuit elements, wherein the at least one demultiplexer is used to store the one or more additional words in one or more available data storage circuit elements of the plurality of data storage circuit elements and used for hashing the message.

A method comprising:

• storing a plurality of words in a plurality of data storage circuit elements in an array, wherein the plurality of words readable as bit line data are to be used for hashing a message, wherein a data storage circuit element of the plurality of data storage circuit elements stores a word of the plurality of words during hashing of the message, wherein hashing the message includes using at least one demultiplexer and at least one multiplexer to simulate shifting of the word without shifting the word to any other data storage circuit element of the plurality of data storage circuit elements, and wherein the at least one multiplexer receives input from one or more bit lines associated with the plurality of data storage circuit elements;
• receiving a clock input from a clock circuit element;
• selecting, using one or more combinational logic circuit elements, specified data storage circuit elements of the plurality of data storage circuit elements based on the clock input, wherein the one or more combinational logic circuit elements cause the at least one multiplexer to select the specified data storage circuit elements according to a specified order that changes throughout hashing the message;
• generating one or more additional words based on input into one or more computational operators of specified words from the specified data storage circuit elements that are selected by the one or more combinational logic circuit elements;
• and
• storing, using the at least one demultiplexer, the one or more additional words in one or more available data storage circuit elements of the plurality of data storage circuit elements, wherein the one or more additional words are used for hashing the message.