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US 12,634,105 B2Granted
Power efficient circuits and methods for phase alignment
AssigneeRambus Inc.
InventorsPavan Kumar Kasibhatla, Jitendra Mishra
Life of this patent
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Abstract
A timing-calibration circuit uses an active phase interpolator to calibrate clock delays through a number of passive fractional delay elements. The timing-calibration circuit minimizes system-wide power consumption by limiting the number and usage of active phase interpolators for delay adjustment in favor of the passive fractional delay elements.
Claims19
A clock-generation circuit, including:
- a phase interpolator issuing a phase-interpolated clock signal;
- and
- a fractional-delay circuit receiving the phase-interpolated clock signal, the fractional-delay circuit having:
- first passive delay element, controlled by a first delay-control signal, issuing a first fractional-delay clock signal phase offset by a first fraction of the period of the phase-interpolated clock signal;
- and
- second passive delay element, controlled by a second delay-control signal, issuing a second fractional-delay clock signal phase offset by a second fraction of the period of the phase-interpolated clock signal;
- wherein the phase interpolator is powered on to calibrate the first and second passive delay elements and powered off after calibration.
4 more elements
An integrated-circuit (IC) module comprising:
- a printed-circuit board (PCB) with signal traces;
- and
- at least one IC component including:
- a phase interpolator issuing a phase-interpolated clock signal;
- and
- a fractional-delay circuit receiving the phase-interpolated clock signal, with a first passive delay element, controlled by a first delay-control signal, issuing a first fractional-delay clock signal;
- and a second passive delay element, controlled by a second delay-control signal, issuing a second fractional-delay clock signal;
- wherein the phase interpolator is powered on to calibrate the first and second passive delay elements and powered off after calibration.
5 more elements
A method comprising:
- interpolating between phases of a reference clock signal via a phase interpolator and thereby producing an interpolated clock signal;
- delaying the reference clock signal by N+1 phase delays via respective N+1 passive delay elements and thereby producing N+1 delayed clock signals;
- phase aligning each of the delayed clock signals with the interpolated clock signal;
- and
- detecting phase alignments between the delayed clock signals and the interpolated clock signal and responsively ceasing the interpolating.
2 more elements
Dependencies are inferred from the claim text.