Estimating and compensating for hardware clock drift based on synchronization signals

A node in a timing network, wherein the node is configured to receive a plurality of synchronization signals from at least one upstream node in the timing network, the node comprising:

• a hardware clock;
• and
• a processor configured to:
• generate a plurality of time stamps, each of the plurality of time stamps recording a point in time, according to the hardware clock, at which each of the plurality of synchronization signals is received;
• select two subsets of time stamps within the plurality of time stamps, the at least two subsets of time stamps respectively including time stamps at different, non-overlapping points in time according to the hardware clock;
• select two time stamps from the two subsets of time stamps, the two time stamps being apart from each other in order within the plurality of time stamps beyond a threshold distance;
• and
• calculate an estimated period of the hardware clock based on the two time stamps.

A computer-implemented method implemented at a node in a timing network, the node including a hardware clock and a processor configured to estimate a clock period drift, wherein the method comprises, by the processor:

• generating a plurality of time stamps, each of the plurality of time stamps recording a point in time, according to the hardware clock, at which each of a plurality of synchronization signals is received from an upstream node in the timing network according to the hardware clock;
• selecting two subsets of time stamps within the plurality of time stamps, the two subsets of time stamps respectively including time stamps at different, non-overlapping points in time according to the hardware clock;
• selecting two time stamps from the two subsets of time stamps, the two time stamps being apart from each other in order within the plurality of time stamps beyond a threshold distance;
• and
• calculating an estimated period of the hardware clock based on the two time stamps.