Adaptive current generation circuit and method applied to input buffer of high-speed ADC

An adaptive current generation circuit, applied to an input buffer of a high-speed ADC, comprising:

• an inverter drive chain, configured to collect an input analog signal of the input buffer, and convert the input analog signal into a first clock signal;
• a frequency divider, configured to receive the first clock signal, and perform frequency division processing on the first clock signal to obtain a second clock signal;
• a frequency detector, configured to receive a reference clock signal and the second clock signal, and perform frequency detection on the second clock signal to obtain a frequency discrimination output signal;
• a low-pass filter, configured to receive the frequency discrimination output signal, and convert the frequency discrimination output signal into a frequency discrimination voltage in a direct current form;
• a static comparator group, configured to receive the frequency discrimination voltage and N reference voltages having different magnitudes, and separately compare the frequency discrimination voltage with the N reference voltages to obtain N bits of digital codes;
• and
• a controllable current mirror, configured to receive the N bits of the digital codes, and provide a magnitude-adjustable input current for the input buffer under control of the N bits of the digital codes, wherein
• N is an integer greater than or equal to 2.