Phase-locked loop circuit, phase error sign generator and RFIC

A radio-frequency integrated circuit (RFIC) comprising:

• a mixer;
• and
• a local oscillator configured to provide a reference frequency source to the mixer,
• wherein the local oscillator comprises:
• a voltage-controlled oscillator configured to generate an output clock signal;
• a phase detector configured to generate a phase error signal representing a phase difference between a first clock signal based on a reference clock signal and a second clock signal based on the output clock signal;
• a comparator configured to generate a phase error sign signal based on a reference voltage and the phase error signal;
• and
• a reference voltage generation circuit configured to scale first and second sign values of the phase error sign signal based on a fixed gain value and a variable gain value, respectively, and generates the reference voltage based on the scaled first and second sign values.