Hybrid fractional phase-locked loop

A phase-locked loop circuit, comprising:

• a phase detector having a first input configured to receive a reference clock signal, a second input configured to receive a feedback clock signal, and an output;
• a charge pump having an input coupled to the output of the phase detector, and having an output;
• a non-integrating loop filter having an input coupled to the output of the charge pump;
• a voltage adder having a first input coupled to an output of the loop filter, a second input, and an output;
• a voltage-controlled oscillator (VCO) configured to output an output clock signal at a phase and frequency corresponding to a voltage at an output of the voltage adder;
• a feedback circuit having an input coupled to an output of the VCO, the feedback circuit configured to output, to a second input of the phase detector, a feedback clock signal at a frequency divided from the output clock signal by a divisor value;
• and
• frequency control circuitry, having a first input configured to receive the output clock signal, a second input configured to receive the reference clock signal, the frequency control circuitry configured to apply a voltage to the second input of the voltage adder responsive to a comparison of a frequency of the output clock signal with a product of a frequency of the reference clock signal and the divisor value.

A method, comprising:

• detecting a phase difference between an input signal and a feedback signal;
• controlling a charge pump responsive to the detected phase difference;
• filtering an output voltage from the charge pump with a non-integrating filter to produce a first voltage controlled oscillator (VCO) input voltage;
• generating an output signal from a VCO responsive to a sum of the first VCO input voltage and a second VCO input voltage, wherein the sum is generated by a voltage adder;
• generating the feedback signal by dividing down a frequency of the output signal by a divisor value;
• and
• generating the second VCO input voltage responsive to a comparison of a frequency of the output signal with a product of the frequency of the input signal and the divisor value.

A phase-locked loop circuit, comprising:

• a phase detector having a reference clock input, a second input, and an output;
• a charge pump having an input coupled to the output of the phase detector, and having an output;
• a non-integrating loop filter having an input coupled to the output of the charge pump, and having an output;
• a voltage adder having a first input coupled to the output of the loop filter, a second input, and an output;
• a voltage-controlled oscillator (VCO) having an input coupled to the output of the voltage adder, and having an output;
• a first frequency divider having an input coupled to the output of the VCO, and an output coupled to the second input of the phase detector;
• a register;
• a first delta-sigma modulator (DSM) having a first input coupled to the output of the first frequency divider, a second input coupled to an output of the register, and an output coupled to a control input of the first frequency divider, wherein the first DSM is configured to output one of a lower divisor value and a higher divisor value for each cycle of a signal at the reference clock input responsive to contents of the register;
• a second frequency divider, having an input coupled to the output of the VCO, the second frequency divider configured to output a signal at a frequency divided down by a value corresponding to the higher divisor value;
• and
• a counter/comparator having a clock input configured to receive a clock signal corresponding to the signal of the reference clock input, a data input coupled to an output of the second frequency divider, and first and second outputs;
• a first capacitor having a terminal coupled to a power supply terminal;
• a first switch having a first terminal coupled to the first capacitor, a second terminal coupled to the second input of the voltage adder, and a control terminal coupled to a first output of the counter/comparator;
• a second capacitor having a terminal coupled to a common terminal;
• a second switch having a first terminal coupled to the second capacitor, a second terminal coupled to the second input of the voltage adder, and a control terminal coupled to the first output of the counter/comparator;
• and
• a main capacitor having a terminal coupled to a reference voltage terminal and to the second input of the voltage adder;
• a second DSM having an input coupled to the second output of the counter, and having an output;
• a third capacitor having a terminal coupled to the power supply terminal;
• a third switch having a first terminal coupled to the third capacitor, a second terminal coupled to the second input of the voltage adder, and a control terminal coupled to the output of the second DSM;
• a fourth capacitor having a terminal coupled to the common terminal;
• and
• a fourth switch having a first terminal coupled to the fourth capacitor, a second terminal coupled to the second input of the voltage adder, and a control terminal coupled to the output of the second DSM.