Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells

A chip-on-chip package comprising:

• a first semiconductor integrated-circuit (IC) chip comprising:
• a first silicon substrate,
• a first transistor at a top surface of the first silicon substrate,
• a through silicon via (TSV) vertically in the first silicon substrate, wherein the through silicon via (TSV) comprises a first copper layer and a first adhesion metal layer at a sidewall of the first copper layer,
• a first insulating dielectric layer on a bottom surface of the first silicon substrate,
• a first metal bump at a bottom of the first semiconductor integrated-circuit (IC) chip, under a bottom surface of the first insulating dielectric layer and on a bottom surface of the through silicon via (TSV), wherein the first metal bump comprises a second copper layer under the bottom surface of the through silicon via (TSV) and a second adhesion metal layer at a top of the second copper layer, between the second copper layer and the bottom surface of the through silicon via (TSV) and under and in contact with the first copper layer,
• an interconnection scheme over the first silicon substrate, wherein the interconnection scheme comprises a second insulating dielectric layer over the first silicon substrate, a third insulating dielectric layer on a top surface of the second insulating dielectric layer and a first interconnection metal layer comprising a third copper layer and a third adhesion metal layer, wherein the third copper layer has a first portion in a first opening in the second insulating dielectric layer and a second portion in a second opening in the third insulating dielectric layer and over the top surface of the second insulating dielectric layer and the third adhesion metal layer has a first portion at a bottom and sidewall of the first portion of the third copper layer and a second portion at a sidewall of the second portion of the third copper layer, and between the second portion of the third copper layer and the top surface of the second insulating dielectric layer, wherein the first interconnection metal layer has a contact point at a bottom of the first opening and in contact with a top surface of the through silicon via (TSV), wherein the first and second portions of the third copper layer are integral as a part and the first and second portions of the third adhesion metal layer are integral as a part, wherein the interconnection scheme further comprises a second interconnection metal layer over the first interconnection metal layer and third insulating dielectric layer and a fourth insulating dielectric layer at a top of the first semiconductor integrated-circuit (IC) chip and over and on a top surface of the second interconnection metal layer, and
• a plurality of metal contacts each in a third opening in the fourth insulating dielectric layer, on a top surface of the fourth insulating dielectric layer and in contact with the second interconnection metal layer, wherein said each of the plurality of metal contacts comprises a fourth copper layer in and over the third opening and over the top surface of the fourth insulating dielectric layer and a fourth adhesion metal layer at a bottom of the fourth copper layer, between the fourth copper layer and second interconnection metal layer and in contact with the second interconnection metal layer,
• a second semiconductor integrated-circuit (IC) chip over and coupling to the first semiconductor integrated-circuit (IC) chip, wherein the second semiconductor integrated-circuit (IC) chip comprises a second silicon substrate, a second transistor at a surface of the second silicon substrate, a fifth insulating dielectric layer at a bottom of the second semiconductor integrated-circuit (IC) chip and a second metal bump at the bottom of the second semiconductor integrated-circuit (IC) chip, in a fourth opening in the fifth insulating dielectric layer, under a bottom surface of the fifth insulating dielectric layer and bonded to a first metal contact of the plurality of metal contacts;
• and
• a third semiconductor integrated-circuit (IC) chip over and coupling to the first semiconductor integrated-circuit (IC) chip and at a same horizontal level as the second semiconductor integrated-circuit (IC) chip, wherein the third semiconductor integrated-circuit (IC) chip comprises a third silicon substrate, a third transistor at a surface of the third silicon substrate, a sixth insulating dielectric layer at a bottom of the third semiconductor integrated-circuit (IC) chip and a third metal bump at the bottom of the third semiconductor integrated-circuit (IC) chip, in a fifth opening in the sixth insulating dielectric layer, under a bottom surface of the sixth insulating dielectric layer and bonded to a second metal contact of the plurality of metal contacts.