Domino logic circuitry with keeper transistors on backside of integrated circuit die

An integrated circuit (IC) die, comprising:

• a domino logic circuit block comprising a plurality of n-type first field effect transistor (FET) structures within a first device layer and interconnected by first metallization levels on a first side of the first device layer;
• one or more second metallization levels on a second side of the first device layer, opposite the first metallization levels, wherein the second metallization levels are to be coupled to a power supply voltage rail;
• a plurality of p-type keeper FET structures coupled to dynamic nodes of the domino logic circuit block, wherein the keeper FET structures are within a second device layer that is between the first device layer and the second metallization levels and wherein the keeper FET structures are powered through the second metallization levels and comprise a gate terminal that is coupled to a transient small signal source to switch the keeper FET structures from off to on states and back to the off state within one precharge interval of an operational cycle and an output capacitance of the keeper FET structures is to charge the nodes of the domino logic circuit block during an evaluation interval following the precharge interval;
• and
• further comprising a cooling structure to maintain at least some of the first FET structures at a temperature below −70° C. during operation of the dynamic nodes of the domino logic circuit block.