Input buffer circuit having variable threshold circuits

An integrated circuit comprising:

• an asymmetry upper threshold circuit having an upper-branch output node configured to output an upper-branch enabling signal generated from an input voltage signal, wherein the asymmetry upper threshold circuit is configured to set the upper-branch enabling signal to a first upper-branch logic level in response to the input voltage signal rising across a main upper threshold, and configured to set the upper-branch enabling signal to a second upper-branch logic level in response to the input voltage signal falling across a supplementary upper threshold, and wherein the supplementary upper threshold is higher than the main upper threshold;
• an asymmetry lower threshold circuit having a lower-branch output node configured to output a lower-branch enabling signal generated from the input voltage signal, wherein the asymmetry lower threshold circuit is configured to set the lower-branch enabling signal to a first lower-branch logic level in response to the input voltage signal falling across a main lower threshold, and configured to set the lower-branch enabling signal to a second lower-branch logic level in response to the input voltage signal rising across a supplementary lower threshold, and wherein the supplementary lower threshold is lower than the main lower threshold;
• and
• a control circuit configured to change an output voltage signal from a first voltage level to a second voltage level in response to a condition that a logic level of the upper-branch enabling signal and a logic level of the lower-branch enabling signal are changed consecutively, wherein the control circuit includes a buffer output node at an electric connection between a first switch and a second switch.

An integrated circuit comprising:

• an asymmetry upper threshold circuit having an upper-branch output node configured to output an upper-branch enabling signal generated from an input voltage signal, wherein the asymmetry upper threshold circuit is configured to set the upper-branch enabling signal to a first upper-branch logic level in response to the input voltage signal rising across a main upper threshold, and configured to set the upper-branch enabling signal to a second upper-branch logic level in response to the input voltage signal falling across a supplementary upper threshold, and wherein the supplementary upper threshold is higher than the main upper threshold;
• an asymmetry lower threshold circuit having a lower-branch output node configured to output a lower-branch enabling signal generated from the input voltage signal, wherein the asymmetry lower threshold circuit is configured to set the lower-branch enabling signal to a first lower-branch logic level in response to the input voltage signal falling across a main lower threshold, and configured to set the lower-branch enabling signal to a second lower-branch logic level in response to the input voltage signal rising across a supplementary lower threshold, and wherein the supplementary lower threshold is lower than the main lower threshold;
• and
• a control circuit configured to change an output voltage signal from a first voltage level to a second voltage level in response to a condition that a logic level of the upper-branch enabling signal and a logic level of the lower-branch enabling signal are changed consecutively, wherein the control circuit includes a buffer output node configured to generate the output voltage signal which depends on a consecutive change of the upper-branch enabling signal and the lower-branch enabling signal.