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US 12,633,907 B2Granted
Memory device, memory system having the same, and operating method thereof
AssigneeSamsung Electronics Co., Ltd.
InventorYoonjae Choi
Life of this patent
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Abstract
A method of operating a memory device includes receiving a quadrature clock and performing quadrature error correction of the quadrature clock in a non-sequential scheme, wherein the quadrature clock includes a first clock, a second clock, a third clock, and a fourth clock, having a sequential phase.
Claims20
A method of operating a memory device, comprising:
- receiving a first clock, a second clock, a third clock, and a fourth clock, having a sequential phase difference;
- updating a first delay code corresponding to a first delay line while detecting a first phase difference between the third clock and the fourth clock during a first clock cycle;
- updating a fourth delay code corresponding to a fourth delay line according to the first phase difference while detecting a second phase difference between the second clock and the third clock during a second clock cycle;
- updating a third delay code corresponding to a third delay line according to the second phase difference while detecting a third phase difference between the first clock and the second clock during a third clock cycle;
- updating a second delay code corresponding to the fourth delay line according to the third phase difference during a fourth clock cycle;
- and
- detecting a fourth phase difference between the fourth clock and the first clock during a fifth clock cycle.
4 more elements
A memory device comprising:
- a first clock line, a second clock line, a third clock line, and a fourth clock line, respectively outputting a first clock, a second clock, a third clock, and a fourth clock, having a sequential phase difference;
- a multiplexer configured to select a first clock output signal and a second clock output signal from the first to fourth clock lines in response to a select signal;
- a first delay line configured to receive the first clock output signal;
- a second delay line configured to receive the second clock;
- a third delay line configured to receive the third clock;
- a fourth delay line configured to receive the fourth clock;
- a phase detector configured to detect a phase difference between a clock delayed through the first delay line and a clock of the second clock output signal;
- and
- a digital logic configured to generate a delay code corresponding to the phase difference and control a delay line corresponding to the delay code, among the first to four delay lines,
- the digital logic configured to generate the select signal to select two clocks, among the first to fourth clocks, in a non-sequential scheme.
7 more elements
A memory system comprising:
- at least one memory device;
- and
- a memory controller configured to control the at least one memory device,
- the at least one memory device including
- a memory cell array having memory cells connected to wordlines and bitlines;
- a quadrature error correction circuit configured to receive a quadrature clock and correct the quadrature clock;
- a clock generator configured to generate the corrected quadrature clock as an internal clock;
- and
- a control logic configured to control write and read operations of the memory cell array,
- the quadrature error correction circuit is configured to correct the quadrature clock in a non-sequential scheme with one phase detector.
7 more elements
Dependencies are inferred from the claim text.