Low power multibit flip-flop for standard cell library

A multibit flip flop comprising:

• a first stage one-bit flip flop;
• at least one intermediate stage one-bit flip flop;
• and
• a last stage one-bit flip flop, wherein the first stage one-bit flip flop, the at least one intermediate stage one-bit flip flop and the last stage one-bit flip flop are configured to share a common clock signal,
• wherein the first stage one-bit flip flop, the at least one intermediate stage one-bit flip flop and the last stage one-bit flip flop are configured to use an inter cell scan input transfer function in a sequential manner,
• wherein the first stage one-bit flip flop is configured to provide a scan output signal based on a scan input signal provided at an input port of the first stage one-bit flip flop,
• wherein the at least one intermediate stage one-bit flip flop is configured to provide a scan intermediate output signal based on the scan output signal,
• wherein the last stage one-bit flip flop is configured to provide a scan final output signal based on the scan intermediate output signal, and
• wherein the first stage one-bit flip flop comprises a multiplexer and a master latch, wherein the multiplexer comprises a first pull-up circuit and a first pull-down circuit, wherein the multiplexer is configured to provide an input of a scan enable pin to the first pull-up circuit, generate an output, and provide the output to the master latch of the first stage one-bit flip flop.

A method of a multibit flip flop, comprising:

• providing a first stage one-bit flip flop and a second stage one-bit flip flop, wherein the first stage one-bit flip flop and the second stage one-bit flip flop share a common clock signal, and wherein the first stage one-bit flip flop and the second stage one-bit flip flop use an inter cell scan input transfer function in a sequential manner, wherein the first stage one-bit flip flop includes a multiplexer and a master latch, and wherein the multiplexer includes a first pull-up circuit and a first pull-down circuit;
• generating an output of the multiplexer as a scan input signal and providing the scan input signal to an input port of the first stage one-bit flip flop;
• generating a scan output signal based on the scan input signal provided to the input port of the first stage one-bit flip flop;
• and
• generating a scan final output signal based on the scan output signal.