Multi-charge pump structure with related method
AssigneeGlobalFoundries U.S. Inc.
InventorsSiva Kumar Chinthu, Sundar Veerendranath Palle, Vivek Saraswat, Balamurugan Periyasamy
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Abstract
The present disclosure relates to structures including charge pump structures and related methods of operating such structures. A structure of the disclosure includes a first charge pump stage including first branches each connected between an input voltage and ground. The first branches each include first capacitors (C1, C2) connected between first intermediate nodes (Q1, Q1_B) and additional first intermediate nodes (V1, V1_B), respectively. A second charge pump stage includes second branches each connected between second intermediate nodes and additional second intermediate nodes, respectively.
Claims18
A structure comprising:
- a first charge pump stage including first branches each connected between an input voltage node and ground, wherein the first branches each include first capacitors (C1, C2) connected between first intermediate nodes (Q1, Q1_B) and additional first intermediate nodes (V1, V1_B), respectively, and wherein the first charge pump stage further includes:
- two first p-channel field effect transistors connected in series between the additional first intermediate nodes (V1, V1_B), and
- two additional first p-channel field effect transistors connected in series between the first intermediate nodes (Q1, Q1_B),
- an additional first capacitor (C3) connected between the input voltage node and a first output voltage node at a junction between the additional first p-channel field effect transistors, wherein the first output voltage node outputs a first output voltage at a magnitude of approximately two times the input voltage;
- and
- a second charge pump stage including second branches, wherein the second branches each include second capacitors each connected between second intermediate nodes and additional second intermediate nodes, respectively, and wherein the second charge pump stage has a second output voltage node that outputs a second output voltage at a magnitude of approximately three times the input voltage.
A structure comprising:
- a first charge pump stage including first branches each connected between an input voltage node and ground, wherein the first branches each include first capacitors (C1, C2) connected between first intermediate nodes (Q1, Q1_B) and additional first intermediate nodes (V1, V1_B), respectively, and wherein the first charge pump stage further includes:
- two first p-channel field effect transistors connected in series between the additional first intermediate nodes (V1, V1_B), wherein the first p-channel field effect transistors are controlled by a clock signal and an inverted clock signal, respectively, and
- two additional first p-channel field effect transistors connected in series between the first intermediate nodes (Q1, Q1_B) and cross coupled to each other;
- an additional first capacitor (C3) connected between an input voltage node and a first output voltage node at a junction between the additional first p-channel field effect transistors, wherein the first output voltage node outputs a first output voltage at a magnitude of approximately two times the input voltage;
- and
- a second charge pump stage including second branches, wherein the second branches each include second capacitors (C4, C5) connected between second intermediate nodes (Q2, Q2_B) and additional second intermediate nodes (V2, V2_B), respectively, and wherein the second charge pump stage has a second output voltage node that outputs a second output voltage at a magnitude of approximately three times the input voltage.
A method comprising:
- applying an input voltage to a first charge pump stage including first branches each connected between an input terminal and ground, wherein the first branches each include first capacitors (C1, C2) connected between first intermediate nodes (Q1, Q1_B) and additional first intermediate nodes (V1, V1_B), respectively, and the first charge pump further includes two first p-channel field effect transistors connected in series between the additional first intermediate nodes (V1, V1_B) and two additional first p-channel field effect transistors connected in series between the first intermediate nodes (Q1, Q1_B);
- connecting an additional first capacitor (C3) between an input voltage node and a first output voltage node at a junction between the additional first p-channel field effect transistors, wherein applying the input voltage causes the first charge pump stage to output a first output voltage at a magnitude of approximately two times the input voltage;
- and
- outputting a voltage from the first charge pump stage to a second charge pump stage including second branches each connected between second intermediate nodes (Q2, Q2_B) and additional second intermediate nodes (V2, V2_B), respectively, wherein the second branches include second capacitors (C4, C5) connected between second intermediate nodes (Q2, Q2_B) and additional second intermediate nodes (V2, V2_B), and wherein the second charge pump stage outputs a second output voltage at a magnitude of approximately three times the input voltage.
Dependencies are inferred from the claim text.