Method of testing a memory circuit and memory circuit

A method of testing a three dimensional (3D) memory cell array, the method comprising:

• applying a first voltage to word lines of each layer of memory cells in the 3D memory cell array thereby performing a write operation of the 3D memory cell array;
• simultaneously performing a read operation of each memory cell in a first layer of the 3D memory cell array, wherein the simultaneously performing the read operation of each memory cell in the first layer of the 3D memory cell array comprises:
• comparing a first total read current of each memory cell in the first layer of the 3D memory cell array with a first expected read current of each memory cell in the first layer of the 3D memory cell;
• determining that each memory cell in the first layer of the 3D memory cell array has not failed in response to the read operation of the first layer of the 3D memory cell array;
• and
• not replacing at least one failed memory cell in the first layer of the 3D memory cell array with a first spare memory cell, in response to determining that each memory cell in the first layer of the 3D memory cell array has not failed.

A memory circuit, comprising:

• a first memory cell array on a first layer;
• a second memory cell array on a second layer different from the first layer;
• a decoder circuit coupled to the first memory cell array and the second memory cell array by a set of word lines, a set of bit lines or a set of source lines, the decoder circuit configured to simultaneously perform a write operation of each memory cell in the first layer of the first memory cell array;
• and
• a read circuit coupled to at least the first memory cell array or the second memory cell array, the read circuit being configured to simultaneously perform a read operation of each memory cell in the first layer of the first memory cell array, and configured to determine whether a memory cell in the first layer of the first memory cell array has failed in response to the read operation,
• wherein the read circuit configured to simultaneously perform the read operation of each memory cell in the first layer of the first memory cell array comprises the read circuit being further configured to compare a total read current of each memory cell in the first layer of the first memory cell array with an expected total read current of each memory cell in the first layer of the first memory cell array.