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US 12,633,363 B2Granted
Encoded read-only memory and decoder
AssigneeQUALCOMM Incorporated
InventorsChulmin Jung, Anil Chowdary Kota, Kuk-Hwan Kim, Sung Son
Life of this patent
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Abstract
A drain programmed read-only memory includes a plurality of bit lines for each drain-programmed transistor. In addition, the drain-programmed read-only memory includes a pair of ground lines for each drain-programmed transistor. A decoder decodes a plurality of bits from each drain-programmed transistor by determining which bit line (if any) and which ground line is coupled to the drain-programmed transistor.
Claims20
A read-only memory comprising:
- a plurality of transistors arranged into a column;
- a plurality of bit lines, each bit line extending across the column;
- a first ground line extending across the column;
- and
- a second ground line extending across the column, wherein each transistor in the plurality of transistors is configured to encode for a plurality of bits through having a source coupled to the first ground line or to the second ground line and through having a drain coupled to one of the bit lines in the plurality of bit lines or through having a floating drain.
2 more elements
A bitcell for a read-only memory, comprising:
- a semiconductor substrate including a diffusion region configured to form a drain and a source of a first transistor and to form a drain and a source of a second transistor;
- a first word line positioned between the drain and the source of the first transistor;
- a first dummy word line positioned between the drain of the first transistor and the source of the second transistor;
- a second word line positioned between the drain and the source of the second transistor;
- a metal layer above the semiconductor substrate, the metal layer being configured to include a first bit line and a second bit line that both extend from a first side of the bitcell to a second side of the bitcell;
- a first via coupled between either the first bit line or the second bit line and the drain of the second transistor, wherein the drain of the first transistor is configured to float with respect to the first bit line and the second bit line;
- a second via coupled between the source of the first transistor and either a first ground line or a second ground line;
- and
- a third via coupled between the source of the second transistor and either the first ground line or the second ground line.
6 more elements
A read-only memory comprising:
- a plurality of bit lines including a first bit line and a second bit line;
- a first transistor having a drain coupled to the first bit line;
- a decoder configured to determine that the first transistor has its drain coupled to the first bit line to decode a first bit;
- a first ground line;
- and
- a second ground line, wherein the first transistor includes a source coupled to the first ground line, and wherein the decoder is further configured to determine that the first transistor has its source coupled to the first ground line to decode a second bit.
3 more elements
Dependencies are inferred from the claim text.