US 12,633,344 B2Granted

Techniques for parallel memory cell access

AssigneeMicron Technology, Inc.

InventorsPaolo Fantini, Andrea Martinelli, Maurizio Rizzi

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Abstract

Methods, systems, and devices for techniques for parallel memory cell access are described. A memory device may include multiple tiers of memory cells. During a first duration, a first voltage may be applied to a set of word lines coupled with a tier of memory cells to threshold one or more memory cells included in a first subset of memory cells of the tier. During a second duration, a second voltage may be applied to the set of word lines to write a first logic state to the one or more memory cells of the first subset and to threshold one or more memory cells included in a second subset of memory cells of the tier. During a third duration, a third voltage may be applied to the set of word lines to write a second logic state to the one or more memory cells of the second subset.

Claims20

Dependent claims

A memory system, comprising:

a plurality of pillars extending vertically through a plurality of tiers of memory cells, each pillar of the plurality of pillars coupled with two memory cells at each tier of the plurality of tiers;
a plurality of bit lines;
a plurality of sets of pillar selectors, each set of pillar selectors associated with a respective conductive line configured to control activation of the set of pillar selectors, wherein a set of pillar selectors is configured to couple a subset of pillars of the plurality of pillars with the plurality of bit lines based at least in part on being activated;
a plurality of sets of word lines, each tier of memory cells coupled with multiple sets of word lines of the plurality of sets of word lines;
and
one or more controllers coupled with the plurality of bit lines, the plurality of sets of pillar selectors, and the plurality of sets of word lines and operable to cause the memory system to apply a sequence of voltages to a first set of word lines of the plurality of sets of word lines coupled with a first tier of memory cells of the plurality of tiers of memory cells, wherein application of a first voltage of the sequence of voltages to the first set of word lines causes at least one memory cell of a first subset of the first tier of memory cells to be written to a first logic state and at least one memory cell of a second subset of the first tier of memory cells to threshold.

3 more elements

A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:

apply a first sequence of voltages to a first set of word lines coupled with a first tier of memory cells of a plurality of tiers of memory cells, wherein each tier of the plurality of tiers is coupled with two sets of alternating word lines and a plurality of pillars extend vertically through the plurality of tiers, each pillar of the plurality of pillars coupled with a respective bit line of a plurality of bit lines and two memory cells at each tier of the plurality of tiers;
and
apply one or more voltages to the plurality of bit lines,
wherein application of the one or more voltages to the plurality of bit lines and a first voltage of the first sequence of voltages to the first set of word lines causes at least one memory cell of a first subset of the first tier of memory cells to be written to a first logic state and at least one memory cell of a second subset of the first tier of memory cells to threshold.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 18/604,192Filed 13 Mar 2024 · continuation
Priority: 15 Feb 2022
Published: US 2024/0304244 A112 Sep 2024
Granted: 19 May 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

G11C 13/0069
Auxiliary circuits: writing or programming circuits or methods
G11C 16/0433
Comprising cells containing floating gate transistors: comprising cells containing a single floating gate transistor and one or more separate…
G11C 13/0028
Address circuits or decoders: word-line or row circuits
G11C 13/0033
Auxiliary circuits: disturbance prevention or evaluation; Refreshing of disturbed memory data

Family

Application17/651,216Parent of this continuation · filed 15 Feb 2022
US 2024/0304244 A1Pre-grant publication · published 12 Sep 2024
US 11,948,638 B2Parent of this continuation
US 2023/0260576 A1Published application
US 12,633,344 B2This patent

From the US filing history. Foreign family members aren’t listed.