In-memory computation device having an improved current reading circuit and control method

A method for controlling an in-memory computation device that is configured to receive an input signal indicative of a plurality of input values and provide at least one output signal;

• wherein the in-memory computation device comprises a word line activation circuit, a memory array and a digital detector, the digital detector being coupled to the bit line and comprising an integration stage and a counter stage, the memory array comprising a plurality of memory cells coupled to a bit line and coupled each to a respective word line, the memory cells being configured to store each a respective computational weight and to receive each a respective activation signal from the respective word line, wherein a respective cell current flows through each memory cell as a function of the respective activation signal and the respective computational weight, and wherein a bit line current flows through the bit line as a function of a summation of the cell currents;
• the method comprising:
• providing, by the word line activation circuit, a plurality of activation signals to the memory cells, wherein each activation signal is a function of a respective input value;
• and
• performing, by the digital detector, a number of successive sampling iterations;
• wherein each sampling iteration comprises, by the integration stage:
• generating an integration signal indicative of a time integral of the bit line current;
• comparing the integration signal with a sampling threshold;
• and
• resetting the integration signal in response to the integration signal reaching the sampling threshold;
• and
• wherein each sampling iteration further comprises, by the counter stage, updating the at least one output signal in response to the integration signal reaching the sampling threshold.