Bleeder and reset for static random access memory

A memory cell comprising:

• a first logic gate configured to receive a first power supply voltage from a first power supply;
• a first inverter cross coupled with the first logic gate;
• a first access transistor coupled between a first data line and a first node, the first node being between an output of the first logic gate and an input of the first inverter;
• and
• a second access transistor coupled between a second data line and a second node, the second node being between an output of the first inverter and a first input of the first logic gate,
• wherein gate electrodes of the first access transistor and the second access transistor are connected to a first word line,
• wherein the first logic gate is configured to reset the memory cell in response to receiving a reset signal at a second input of the first logic gate when the first power supply is switched off.

A non-transitory computer readable medium storing a digital representation of a circuit comprising:

• a memory cell connected to a first power supply configured to supply a first power supply voltage;
• a first bleeder transistor coupled between a first node of the memory cell and ground;
• a second circuit coupled to a gate electrode of the first bleeder transistor and configured to supply a bleeder signal to control the first bleeder transistor in response to a drop in the first power supply voltage;
• and
• a third transistor coupled between the ground and the first power supply,
• wherein the first bleeder transistor is configured to discharge the memory cell in response to receiving the bleeder signal,
• wherein a first electrode and a gate electrode of the third transistor are electrically coupled to the first power supply and a second electrode of the third transistor is connected to the ground;
• and
• wherein the third transistor is a n-type transistor.