Memory architecture supporting both conventional memory access mode and digital in-memory computation processing mode

A circuit, comprising:

• a memory array including a plurality of sub-arrays, wherein each sub-array includes memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a local bit line connected to the memory cells of the column;
• a word line drive circuit for each row having an output connected to drive the word line of the row;
• a row decoder circuit coupled to the word line drive circuits;
• a control circuit configured to support two modes of memory circuit operation including:
• a first mode where the row decoder circuit actuates only one word line in the memory array during a memory access operation and a second mode where the row decoder circuit simultaneously actuates only one word line per sub-array during an in-memory computation operation;
• an input/output circuit for each column comprising:
• a plurality of bit line inputs coupled to the local bit lines of the sub-arrays;
• a column data output coupled to the plurality of bit line inputs and configured to generate a column data bit for output in the first mode;
• and
• a plurality of sub-array data outputs, where each sub-array data output is coupled to a corresponding one of the plurality of bit line inputs, and configured to generate a plurality of sub-array data bits for output in the second mode;
• and
• a processing circuit configured to receive feature data and perform a computational operation as a function of the feature data and the plurality of sub-array data bits.