Shift register unit, gate drive circuit, and display device

A gate drive circuit, comprising a shift register unit,

• wherein the shift register unit comprises:
• an input module, configured to transmit a signal at an input terminal to a first node in response to a first clock signal;
• a first control module, configured to:
• transmit a first voltage signal to a second node in response to the first clock signal;
• and transmit the first clock signal to the second node in response to the signal at the input terminal;
• a second control module, configured to transmit the first voltage signal to a third node in response to a second clock signal;
• a third control module, configured to transmit a second voltage signal to the third node in response to a signal at the first node;
• a first output module, configured to transmit the second voltage signal to an output terminal in response to a signal at the third node;
• a second output module, configured to transmit the first voltage signal to the output terminal in response to the signal at the first node;
• a first capacitor connected between the first node and a second voltage signal lead;
• a second capacitor connected between a second clock signal lead and the second node;
• and
• a third capacitor connected between the second voltage signal lead and the third node.

A display device, comprising a gate drive circuit, wherein the gate drive circuit comprises a shift register unit, and the shift register unit comprises:

• an input module, configured to transmit a signal at an input terminal to a first node in response to a first clock signal;
• a first control module, configured to:
• transmit a first voltage signal to a second node in response to the first clock signal;
• and transmit the first clock signal to the second node in response to the signal at the input terminal;
• a second control module, configured to transmit the first voltage signal to a third node in response to a second clock signal;
• a third control module, configured to transmit a second voltage signal to the third node in response to a signal at the first node;
• a first output module, configured to transmit the second voltage signal to an output terminal in response to a signal at the third node;
• a second output module, configured to transmit the first voltage signal to the output terminal in response to the signal at the first node;
• a first capacitor connected between the first node and a second voltage signal lead;
• a second capacitor connected between a second clock signal lead and the second node;
• and
• a third capacitor connected between the second voltage signal lead and the third node.