Driving circuit, driving method, and display panel

A driving method of a driving circuit, wherein the driving circuit comprises:

• a timing controller comprising a first pin;
• a power management chip comprising a second pin;
• a first shared discharge rod, wherein the power management chip is electrically connected to the first shared discharge rod;
• a second shared discharge rod, wherein the power management chip is electrically connected to the second shared discharge rod;
• wherein the first pin is electrically connected to the second pin, the power management chip is configured to output voltages with opposite polarities to the first shared discharge rod and the second shared discharge rod at the same time, the power management chip is configured to invert a voltage of the first shared discharge rod and a voltage of the second shared discharge rod under a control of a level signal of the first pin in a blanking time interval of each frame;
• wherein the method comprises the following steps:
• wherein in the blanking time interval of each frame, the timing controller controls the level signal of the first pin to switch between a high level and a low level;
• wherein the power management chip is configured to invert the voltage of the first shared discharge rod and the voltage of the second shared discharge rod under the control of the level signal of the first pin in the blanking time interval of each frame;
• in the blanking time interval of each frame, when the level signal of the first pin is at the high level, the power management chip outputs a negative voltage to the first shared discharge rod, and the power management chip outputs a positive voltage to the second shared discharge rod;
• when the level signal of the first pin is at the low level, the power management chip outputs the positive voltage to the first shared discharge rod, and the power management chip outputs the negative voltage to the second shared discharge rod.

A display panel, wherein the display panel comprises a plurality of sub-pixels arranged in an array and a driving circuit, wherein the driving circuit comprises:

• a timing controller comprising a first pin;
• a power management chip comprising a second pin;
• a first shared discharge rod, wherein the power management chip is electrically connected to the first shared discharge rod;
• a second shared discharge rod, wherein the power management chip is electrically connected to the second shared discharge rod;
• wherein the first pin is electrically connected to the second pin, the power management chip is configured to output voltages with opposite polarities to the first shared discharge rod and the second shared discharge rod at the same time, the power management chip is configured to invert a voltage of the first shared discharge rod and a voltage of the second shared discharge rod under a control of a level signal of the first pin in a blanking time interval of each frame;
• wherein the first shared discharge rod of the driving circuit is electrically connected to the sub-pixels of a first column, and the second shared discharge rod of the driving circuit is electrically connected to the sub-pixels of a second column;
• wherein the timing controller comprises:
• a controller;
• a pulse signal generator electrically connected to the controller;
• and
• a register, wherein the controller is electrically connected to the register, and the register is electrically connected to the first pin;
• wherein the power management chip further comprises:
• a decoder, wherein an input terminal of the decoder is electrically connected to the second pin;
• and
• a voltage conversion circuit, wherein the voltage conversion circuit comprises a first signal control terminal, a power supply access terminal, a first voltage output terminal, and a second voltage output terminal, the first signal control terminal is electrically connected to an output terminal of the decoder, the first voltage output terminal is electrically connected to the first shared discharge rod, and the second voltage output terminal is electrically connected to the second shared discharge rod.