Circuit implementation on processing circuitry
AssigneeAltera Corporation
InventorsKrishna Kumar Nagar, Nathan Krueger, Yi Peng, Brandon Lewis Gordon, Anand Venkitasubramani
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Abstract
Systems or methods of the present disclosure may provide efficient circuit implementation on processing circuitry. The processing circuitry may include a processor, a programmable hardware, or both. The systems and methods may include determining and removing unused and/or redundant portions of predefined software and hardware description instructions before implementing associated circuitry. The implemented circuitry may perform various functions including parsing, pipelining, deparsing, temporary storage and combining, math operations, or a combination thereof, among other things.
Claims20
A data processing system, comprising:
- a memory storing code describing a plurality of predefined instruction set architecture (ISA) units, wherein each ISA unit comprises one or more instructions;
- and
- a first processor executing instructions to:
- receive software associated with performing a function using a second processor;
- determine one or more predefined ISA units to be used by the second processor based on the software;
- determine one or more extraneous instructions of at least one predefined ISA unit of the one or more predefined ISA units based at least in part on the software;
- and
- generate a design for a processor circuit of the second processor by removing the one or more extraneous instructions to cause the second processor to use a reduced-set ISA unit rather than the at least one predefined ISA unit to perform the function by implementing the design.
A method, comprising:
- storing, by a first processor, code describing a plurality of predefined instruction set architecture (ISA) units, wherein each ISA unit comprises one or more instructions;
- receiving, by the first processor, software associated with performing a function on a second processor;
- determining, by the first processor, one or more predefined ISA units of the plurality of predefined ISA units to be used by the second processor based at least in part on the received software;
- and
- generating, by the first processor, a modified ISA unit based on replacing at least one instruction of at least one predefined ISA unit of the one or more predefined ISA units with one or more alternative instructions to replace a function of the at least one instruction with a function of the one or more alternative instructions when executed on the second processor.
A non-transitory computer-readable medium comprising computer-executable instructions that, when executed, are configured to cause a first processor to:
- receive program code associated with performing a first function;
- provide first configuration settings and control parameters to a memory based on the program code, wherein
- the first configuration settings are associated with selecting at least a first predefined register transfer level (RTL) block of one or more predefined RTL blocks stored on the memory, and
- the control parameters are associated with options associated with removing unused portions of at least the first predefined RTL block based on the program code;
- and
- generate at least one modified RTL block by removing at least a portion of at least the first predefined RTL block based on the control parameters;
- and
- output a design to be implemented in a programmable logic device using the at least one modified RTL block.
Dependencies are inferred from the claim text.