Semiconductor memory device and memory system including the same

A memory system comprising:

• a semiconductor memory device;
• and
• a memory controller configured to control the semiconductor memory device,
• wherein the semiconductor memory device comprises:
• a memory cell array comprising a plurality of memory cell rows, each of the plurality of memory cell rows comprising a plurality of memory cells;
• an error correction code (ECC) engine configured to perform an ECC decoding on data read from the memory cell array and generate an error generation signal based on the ECC decoding;
• an error check and scrub (ECS) circuit configured to generate scrubbing addresses for performing a scrubbing operation in an ECS mode and output at least one of the scrubbing addresses as an error address based on the error generation signal, wherein the error generation signal corresponds to a detection of a number of error bits in excess of a predetermined threshold;
• a row hammer management circuit configured to:
• in the ECS mode, store an error flag with a first logic level in a portion of count cells to store count data, of each of one or more adjacent memory cell rows which are physically adjacent to a weak memory cell row corresponding to the error address from among the plurality of memory cell rows;
• and
• in a normal mode, compare counted values indicating a number of times of access associated with each of the plurality of memory cell rows with different reference number of times based on a logic level of the error flag and output a hammer address designating a first memory cell row, which is intensively accessed, from among the plurality of memory cell rows based on the comparison;
• and
• a refresh control circuit configured to receive the hammer address and perform a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to the first memory cell row corresponding to the hammer address.

A semiconductor memory device comprising:

• a memory cell array comprising a plurality of memory cell rows, each comprising a plurality of memory cells;
• an error correction code (ECC) engine configured to perform an ECC decoding on data read from the memory cell array and generate an error generation signal based on the ECC decoding, wherein the error generation signal corresponds to a detection of a number of error bits in excess of a predetermined threshold;
• an error check and scrub (ECS) circuit configured to generate scrubbing addresses for performing a scrubbing operation in an ECS mode and output at least one of the scrubbing addresses as an error address based on the error generation signal;
• a row hammer management circuit configured to:
• in the ECS mode, store an error flag with a first logic level in a portion of count cells to store count data, of each of one or more adjacent memory cell rows which are physically adjacent to a weak memory cell row corresponding to the error address from among the plurality of memory cell rows, and
• in a normal mode, compare counted values indicating a number of times of access associated with each of the plurality of memory cell rows with different reference number of times based on a logic level of the error flag and output a hammer address designating a memory cell row, which is intensively accessed, from among the plurality of memory cell rows based on the comparison;
• and
• a refresh control circuit configured to receive the hammer address and perform a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to the memory cell row corresponding to the hammer address,
• wherein the row hammer management circuit is further configured to:
• receive the error address in the ECS mode,
• sequentially access a first adjacent memory cell row and a second adjacent memory cell row which are physically adjacent to the weak memory cell row corresponding to the error address, and
• store the error flag with the first logic level in respective count cells of each of the first adjacent memory cell row and the second adjacent memory cell row.