Coherent communication between a processor core and an accelerator

A computer-implemented method, comprising:

• selecting, by a system operatively coupled to a processor, an accelerator to execute one or more functions related to a program being executed by a processor core;
• and
• transmitting, by the system, an address associated with a cache to the accelerator, wherein the address is transmitted within a start command from the processor core to the accelerator via a signaling bus that is directly connected between the processor core and the accelerator, wherein the cache is accessible to both the processor core and the accelerator, and wherein the address is employable by the accelerator to install one or more messages in the cache via non-cached stores to communicate a running state of the accelerator to the processor core during execution of the one or more functions.

A computer program product for communication between a processor core and an accelerator, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:

• select, by the processor, the accelerator to execute one or more functions related to a program being executed by the processor core;
• and
• transmit, by the processor, an address associated with a cache to the accelerator, wherein the address is transmitted within a start command from the processor core to the accelerator via a signaling bus that is directly connected between the processor core and the accelerator, wherein the cache is accessible to both the processor core and the accelerator, and wherein the address is employable by the accelerator to install one or more messages in the cache via non-cached stores to communicate a running state of the accelerator to the processor core during execution of the one or more functions.