I/O agent

A method, comprising:

• implementing, by input/output (I/O) agent circuitry of a system, coherency mechanisms to bridge one or more peripheral components to an interconnect of the system so that the one or more peripheral components can interact with circuitry that is coupled to the interconnect, including memory controller circuitry that is configured to couple to a memory and manage access to data that is stored in the memory;
• receiving, by the I/O agent circuitry, read and write requests from the one or more peripheral components;
• and
• issuing, by the I/O agent circuitry to the memory controller circuitry, a request for exclusive read ownership of a first cache line for a first read request of the read and write requests;
• after issuance of the request for exclusive read ownership of the first cache line, issuing, by the I/O agent circuitry to the memory controller circuitry, a request for exclusive read ownership of a second cache line for a second read request;
• receiving, by the I/O agent circuitry, exclusive read ownership of the second cache line before receiving exclusive read ownership of the first cache line;
• and
• as part of processing the read and write requests, the I/O agent circuitry caching data for at least one of the one or more peripheral components that does not include a cache.

A non-transitory computer readable medium having stored thereon design information that specifies a circuit design in a format recognized by a fabrication system that is configured to use the design information to fabricate a hardware integrated circuit that comprises:

• memory controller circuitry configured to couple to a memory and manage access to data that is stored in the memory;
• processor circuitry configured to retrieve instructions from the memory via the memory controller circuitry and execute the instructions;
• an interconnect configured to couple the memory controller circuitry to the processor circuitry;
• input/output (I/O) agent circuitry that is coupled to one or more peripheral components and the interconnect, wherein the I/O agent circuitry is configured to:
• implement coherency mechanisms to bridge one or more peripheral components to the interconnect so that the one or more peripheral components can interact with circuitry that is coupled to the interconnect, wherein the one or more peripheral components are configured to issue read and write requests associated with the memory;
• receive the read and write requests;
• and
• issue, to the memory controller circuitry, a request for exclusive read ownership of a first cache line for a first read request of the read and write requests;
• after issuance of the request for exclusive read ownership of the first cache line, issue, to the memory controller circuitry, a request for exclusive read ownership of a second cache line for a second read request;
• receive exclusive read ownership of the second cache line before receiving exclusive read ownership of the first cache line;
• and
• obtain exclusive write ownership for at least one of the write requests.