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US 12,632,383 B2Granted
Modification of page tables in shared memory modules
OwnerDmitri Yudanovinventor
Life of this patent
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Abstract
A memory module system with a global shared context. A memory module system can include a plurality of memory modules and at least one processor, which can implement the global shared context. The memory modules of the system can provide the global shared context at least in part by providing an address space shared between the modules and applications running on the modules. The address space sharing can be achieved by having logical addresses global to the modules, and each logical address can be associated with a certain physical address of a specific module.
Claims20
A system, comprising:
- a plurality of memory modules inter-connected to provide a physical memory, each respective memory module of the plurality of memory modules comprising a plurality of partitions of the physical memory, wherein a partition of the plurality of partitions is associated with at least one physical memory address;
- a plurality of processors, wherein each processor of the plurality of processors is associated with the respective memory module of the plurality of memory modules;
- and
- at least one processor of the plurality of processors configured to:
- execute code, wherein execution of the code causes the at least one processor to access a virtual memory address, wherein only a single processor of the plurality of processors is configured to initially execute the code;
- map the virtual memory address to a shared memory address in a logical memory space shared between the plurality of processors in the plurality of memory modules;
- map the shared memory address to a physical memory address of the partition of the plurality of partitions;
- and
- send, based on the physical memory address and after the initial execution of the code by the single processor, to another processor of the plurality of processors that is associated with the physical memory address, data for continuing to execute a program code at least partially executed by the at least one processor.
6 more elements
A method comprising:
- executing, by a processor in a memory module among a plurality of memory modules inter-connected to provide a physical memory, code to cause the processor to access a virtual memory address, wherein each of the plurality of memory modules has one or more processors;
- mapping, by the processor, the virtual memory address to a shared memory address in a logical memory space shared between processors in the plurality of memory modules inter-connected to provide the physical memory, the memory module of the plurality of memory modules comprising a plurality of partitions of the physical memory, wherein a partition of the plurality of partitions is associated with at least one physical memory address;
- mapping, by the processor, the shared memory address to a physical memory address of the partition of the plurality of partitions;
- and
- sending, by the processor based on the physical memory address and after executing the code by the processor, to another processor of the processors that is associated with the physical memory address, data for continuing to execute a program code at least partially executed by the processor.
2 more elements
A non-transitory computer-readable storage medium for tangibly storing computer program instructions which when executed by a processor, cause the processor to perform a method, comprising:
- executing, by the processor in a memory module among a plurality of memory modules inter-connected to provide a physical memory, code to cause the processor to access a virtual memory address, wherein each of the plurality of memory modules has one or more processors;
- mapping, by the processor, the virtual memory address to a shared memory address in a logical memory space shared between processors in the plurality of memory modules inter-connected to provide the physical memory, the memory module of the plurality of memory modules comprising a plurality of partitions of the physical memory, wherein a partition of the plurality of partitions is associated with at least one physical memory address;
- mapping, by the processor, the shared memory address to a physical memory address of the partition of the plurality of partitions;
- and
- sending, by the processor based on the physical memory address and after execution of the code by the processor, to another processor of the processors that is associated with the physical memory address, data for continuing to execute a program code at least partially executed by the processor.
2 more elements
Dependencies are inferred from the claim text.