Computer system with reconfigurable processors

A computer system, comprising:

• an array of reconfigurable processing units;
• wherein the array is configured into a plurality of execution fragment resource groups (EFRGs) for executing fragments of a data processing operation, the fragments having quiesce boundaries;
• wherein an execution fragment comprises, in a coarse-grained reconfigurable architecture CGRA, a subset of operations in a control and data flow graph of the data processing operation;
• and
• a quiesce controller for distributing quiesce control signals to quiesce logic associated with the reconfigurable processing units in the array, and for receiving quiesce ready signals from the plurality of execution fragment resource groups EFRGs,
• wherein the quiesce boundaries use configuration data defining sets of configured states of execution in the reconfigurable processing units configured to execute the execution fragments.