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US 12,632,262 B2Granted
Programmable event testing
AssigneeTexas Instruments Incorporated
InventorsKai Chirca, Timothy D. Anderson
Life of this patent
Estimating the term…
Abstract
A method includes executing software code comprising a plurality of execute packets; responsive to an execute packet of the software code being executed by a data processor core, advancing a value of a test counter register; and responsive to the value of the test counter register being equal to a terminal value, triggering an event to be handled by the software code.
Claims18
An integrated circuit device comprising:
- an event test circuit that includes:
- a test counter register configured to store a count of packets of instructions associated with software code being tested on the integrated circuit device;
- a first register configured to store an identifier of an event;
- and
- a second register configured to store a first priority level of the event for a first set of one or more packets of instructions and to store a second priority level of the event for a second set of one or more packets of instructions, wherein the first and second sets of packets of instructions are part of the count, wherein the packets of instructions associated with the software code has a third priority level and the first priority level is higher than the third priority level and the second priority level is lower than the third priority level;
- wherein the event test circuit is configured to:
- trigger the event associated with the identifier based on the count of packets and when the count is associated with a packet of instructions corresponding to the first set having the first priority level for the event;
- and
- not trigger the event associated with the identifier based on the count of packets and when the count is associated with a packet of instructions corresponding to the second set having the second priority level for the event.
6 more elements
An integrated circuit device that includes:
- a processor core configured to execute a program that includes a set of instructions associated with software code being tested on the integrated circuit device, wherein the software code has a first priority level and the set of instructions is arranged into a set of at least a first set of packets and a second set of packets;
- and
- an event test circuit coupled to the processor core that includes:
- a test counter register configured to store a count of packets;
- a first register configured to store an identifier of an event;
- and
- a second register configured to store a second priority level of the event for the first set of packets and to store a third priority level of the event for the second set of packets, wherein the first priority level is lower than the second priority level but higher than the third priority level;
- wherein the event test circuit is configured to:
- adjust the count of packets based on execution of a packet of the set of packets;
- and
- based on the count of packets and the priority of the event, determine whether to trigger the event, wherein the event is triggered when the count of the packets corresponds to a packet of the first set of packets for which the second register stores the second priority level and is not triggered when the count of packets corresponds to a packet of the second set of packets for which the second register stores the third priority level.
8 more elements
A method comprising:
- for a plurality of instruction packets each having a first priority level and corresponding to software code being tested using a processor core, associating a second priority level for an event with a first set of the instruction packets and associating a third priority level for the event with a second set of the instruction packets, wherein the first priority level is lower than the second priority level and the first priority level is higher than the third priority level;
- executing an instruction packet by a processor core;
- based on the executing of the instruction packet, adjusting a test count of instruction packets;
- performing an event based on the test count of instruction packets and on whether the instruction packet associated with the test count is part of the first set of instructions packets associated with the second priority level;
- and
- not performing the event based on the test count of the instruction packets and on whether the instruction packet associated with the test count is part of the second set of instruction packets associated with the third priority level.
3 more elements
Dependencies are inferred from the claim text.