System and architecture neural network accelerator including filter circuit

A system, comprising:

• a memory to store data;
• a processor, communicatively coupled to the memory, to execute a neural network application comprising filter operations using the data;
• and
• an accelerator circuit comprising:
• an internal memory;
• a filter circuit block comprising a plurality of circuit stripes, each circuit stripe comprising:
• a filter processor;
• a plurality of filter circuits;
• and
• a slice of the internal memory assigned to the plurality of filter circuits,
• wherein the filter processor is to execute a filter instruction, to:
• read data values from the internal memory based on a first memory address;
• for each circuit stripe:
• load the data values in weight registers and input registers associated with the plurality of filter circuits of the circuit stripe to generate a plurality of filter results;
• and
• write a result generated using the plurality of filter circuits in the internal memory at a second memory address;
• an input circuit block comprises an input processor, a first instruction memory, a first data memory, and a first program counter (PC), wherein the first instruction memory is to store first instructions of a first task specified according to a first instruction set architecture (ISA) of the input processor, wherein the first PC is to store an address of a current first instruction to be executed by a first processor, and wherein the input processor is to execute the first instructions using first data stored in the first data memory to perform the first task;
• the filter circuit block comprising a second instruction memory, a second data memory, and a second PC, wherein the second instruction memory is to store second instructions of a second task specified according to a second ISA of the filter processor, wherein the second PC is to store an address of a current second instruction to be executed by a second processor, and wherein the filter processor is to execute the second instructions using second data stored in the second data memory to perform the second task;
• a post-processing circuit block comprising a post-processing processor, a third instruction memory, a third data memory, and a third PC, wherein the third instruction memory is to store third instructions of a third task specified according to a third ISA of the post-processing processor, wherein the third PC is to store an address of a current third instruction to be executed by a third processor, and wherein the post-processing processor is to execute the third instructions using third data stored in the third data memory to perform the third task;
• and
• an output circuit block comprising an output processor, a fourth instruction memory, a fourth data memory, and a fourth PC, wherein the fourth instruction memory is to store fourth instructions of a fourth task specified according to a fourth ISA of the output processor, wherein the fourth PC is to store an address of a current fourth instruction to be executed by a fourth processor, and wherein the output processor is to execute the fourth instructions using fourth data stored in the fourth data memory to perform the fourth task.

A method comprising:

• receiving, by an accelerator circuit, a task comprising a filter instruction from a processor, wherein the accelerator circuit comprises a filter circuit block comprising a plurality of circuit stripes, each circuit stripe comprising a filter engine, a plurality of filter circuits, an input circuit block comprising an input processor, a first instruction memory, a first data memory, and a first program counter (PC), wherein the first instruction memory is to store first instructions of a first task specified according to a first instruction set architecture (ISA) of the input processor, wherein the first PC is to store an address of a current first instruction to be executed by a first processor, and wherein the input processor is to execute the first instructions using first data stored in the first data memory to perform the first task,
• the filter circuit block comprising a second instruction memory, a second data memory, and a second PC, wherein the second instruction memory is to store second instructions of a second task specified according to a second ISA of the filter processor, wherein the second PC is to store an address of a current second instruction to be executed by a second processor, and wherein the filter processor is to execute the second instructions using second data stored in the second data memory to perform the second task,
• a post-processing circuit block comprising a post-processing processor, a third instruction memory, a third data memory, a third PC, wherein the third instruction memory is to store third instructions of a third task specified according to a third ISA of the post-processing processor, wherein the third PC is to store an address of a current third instruction to be executed by a third processor, and wherein the post-processing processor is to execute the third instructions using third data stored in the third data memory to perform the third task;
• an output circuit block comprising an output processor, a fourth instruction memory, a fourth data memory, a fourth PC, wherein the fourth instruction memory is to store fourth instructions of a fourth task specified according to a fourth ISA of the output processor, wherein the fourth PC is to store an address of a current fourth instruction to be executed by a fourth processor, and wherein the output processor is to execute the fourth instructions using fourth data stored in the fourth data memory to perform the fourth task,
• and a slice of an internal memory assigned to the plurality of filter circuits;
• reading data values from the internal memory of the accelerator circuit starting from a first memory address;
• for each of the plurality of circuit stripes, loading the data values in weight registers and input registers associated with a plurality of filter circuits to generate a plurality of filter results;
• and
• writing a result generated using the plurality of filter circuits in the internal memory at a second memory address.